1 /* 2 * Copyright (c) 2019 Red Hat, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2 or later, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef HW_I386_X86_H 18 #define HW_I386_X86_H 19 20 #include "qemu-common.h" 21 #include "exec/hwaddr.h" 22 #include "qemu/notify.h" 23 24 #include "hw/i386/topology.h" 25 #include "hw/boards.h" 26 #include "hw/nmi.h" 27 #include "hw/isa/isa.h" 28 #include "hw/i386/ioapic.h" 29 30 typedef struct { 31 /*< private >*/ 32 MachineClass parent; 33 34 /*< public >*/ 35 36 /* TSC rate migration: */ 37 bool save_tsc_khz; 38 /* Enables contiguous-apic-ID mode */ 39 bool compat_apic_id_mode; 40 } X86MachineClass; 41 42 typedef struct { 43 /*< private >*/ 44 MachineState parent; 45 46 /*< public >*/ 47 48 /* Pointers to devices and objects: */ 49 ISADevice *rtc; 50 FWCfgState *fw_cfg; 51 qemu_irq *gsi; 52 GMappedFile *initrd_mapped_file; 53 54 /* Configuration options: */ 55 uint64_t max_ram_below_4g; 56 57 /* RAM information (sizes, addresses, configuration): */ 58 ram_addr_t below_4g_mem_size, above_4g_mem_size; 59 60 /* CPU and apic information: */ 61 bool apic_xrupt_override; 62 unsigned apic_id_limit; 63 uint16_t boot_cpus; 64 unsigned smp_dies; 65 66 OnOffAuto smm; 67 68 /* 69 * Address space used by IOAPIC device. All IOAPIC interrupts 70 * will be translated to MSI messages in the address space. 71 */ 72 AddressSpace *ioapic_as; 73 } X86MachineState; 74 75 #define X86_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 76 #define X86_MACHINE_SMM "smm" 77 78 #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86") 79 #define X86_MACHINE(obj) \ 80 OBJECT_CHECK(X86MachineState, (obj), TYPE_X86_MACHINE) 81 #define X86_MACHINE_GET_CLASS(obj) \ 82 OBJECT_GET_CLASS(X86MachineClass, obj, TYPE_X86_MACHINE) 83 #define X86_MACHINE_CLASS(class) \ 84 OBJECT_CLASS_CHECK(X86MachineClass, class, TYPE_X86_MACHINE) 85 86 void init_topo_info(X86CPUTopoInfo *topo_info, const X86MachineState *x86ms); 87 88 uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms, 89 unsigned int cpu_index); 90 91 void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp); 92 void x86_cpus_init(X86MachineState *pcms, int default_cpu_version); 93 CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms, 94 unsigned cpu_index); 95 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx); 96 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms); 97 98 void x86_bios_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw); 99 100 void x86_load_linux(X86MachineState *x86ms, 101 FWCfgState *fw_cfg, 102 int acpi_data_size, 103 bool pvh_enabled, 104 bool linuxboot_dma_enabled); 105 106 bool x86_machine_is_smm_enabled(X86MachineState *x86ms); 107 108 /* Global System Interrupts */ 109 110 #define GSI_NUM_PINS IOAPIC_NUM_PINS 111 112 typedef struct GSIState { 113 qemu_irq i8259_irq[ISA_NUM_IRQS]; 114 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 115 } GSIState; 116 117 qemu_irq x86_allocate_cpu_irq(void); 118 void gsi_handler(void *opaque, int n, int level); 119 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 120 121 /* hpet.c */ 122 extern int no_hpet; 123 124 #endif 125