1 /* 2 * Copyright (c) 2019 Red Hat, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2 or later, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef HW_I386_X86_H 18 #define HW_I386_X86_H 19 20 #include "exec/hwaddr.h" 21 22 #include "hw/boards.h" 23 #include "hw/intc/ioapic.h" 24 #include "hw/isa/isa.h" 25 #include "qom/object.h" 26 27 struct X86MachineClass { 28 /*< private >*/ 29 MachineClass parent; 30 31 /*< public >*/ 32 33 /* TSC rate migration: */ 34 bool save_tsc_khz; 35 /* use DMA capable linuxboot option rom */ 36 bool fwcfg_dma_enabled; 37 /* CPU and apic information: */ 38 bool apic_xrupt_override; 39 }; 40 41 struct X86MachineState { 42 /*< private >*/ 43 MachineState parent; 44 45 /*< public >*/ 46 47 /* Pointers to devices and objects: */ 48 ISADevice *rtc; 49 FWCfgState *fw_cfg; 50 qemu_irq *gsi; 51 DeviceState *ioapic2; 52 GMappedFile *initrd_mapped_file; 53 HotplugHandler *acpi_dev; 54 55 /* RAM information (sizes, addresses, configuration): */ 56 ram_addr_t below_4g_mem_size, above_4g_mem_size; 57 58 /* Start address of the initial RAM above 4G */ 59 uint64_t above_4g_mem_start; 60 61 /* CPU and apic information: */ 62 unsigned pci_irq_mask; 63 unsigned apic_id_limit; 64 uint16_t boot_cpus; 65 SgxEPCList *sgx_epc_list; 66 67 OnOffAuto smm; 68 OnOffAuto acpi; 69 OnOffAuto pit; 70 OnOffAuto pic; 71 72 char *oem_id; 73 char *oem_table_id; 74 /* 75 * Address space used by IOAPIC device. All IOAPIC interrupts 76 * will be translated to MSI messages in the address space. 77 */ 78 AddressSpace *ioapic_as; 79 80 /* 81 * Ratelimit enforced on detected bus locks in guest. 82 * The default value of the bus_lock_ratelimit is 0 per second, 83 * which means no limitation on the guest's bus locks. 84 */ 85 uint64_t bus_lock_ratelimit; 86 }; 87 88 #define X86_MACHINE_SMM "smm" 89 #define X86_MACHINE_ACPI "acpi" 90 #define X86_MACHINE_PIT "pit" 91 #define X86_MACHINE_PIC "pic" 92 #define X86_MACHINE_OEM_ID "x-oem-id" 93 #define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id" 94 #define X86_MACHINE_BUS_LOCK_RATELIMIT "bus-lock-ratelimit" 95 96 #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86") 97 OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE) 98 99 uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms, 100 unsigned int cpu_index); 101 102 void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp); 103 void x86_cpus_init(X86MachineState *pcms, int default_cpu_version); 104 CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms, 105 unsigned cpu_index); 106 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx); 107 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms); 108 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx); 109 void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count); 110 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, 111 DeviceState *dev, Error **errp); 112 void x86_cpu_plug(HotplugHandler *hotplug_dev, 113 DeviceState *dev, Error **errp); 114 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 115 DeviceState *dev, Error **errp); 116 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, 117 DeviceState *dev, Error **errp); 118 119 void x86_bios_rom_init(MachineState *ms, const char *default_firmware, 120 MemoryRegion *rom_memory, bool isapc_ram_fw); 121 122 void x86_load_linux(X86MachineState *x86ms, 123 FWCfgState *fw_cfg, 124 int acpi_data_size, 125 bool pvh_enabled); 126 127 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms); 128 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms); 129 130 /* Global System Interrupts */ 131 132 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 133 134 typedef struct GSIState { 135 qemu_irq i8259_irq[ISA_NUM_IRQS]; 136 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 137 qemu_irq ioapic2_irq[IOAPIC_NUM_PINS]; 138 } GSIState; 139 140 qemu_irq x86_allocate_cpu_irq(void); 141 void gsi_handler(void *opaque, int n, int level); 142 void ioapic_init_gsi(GSIState *gsi_state, Object *parent); 143 DeviceState *ioapic_init_secondary(GSIState *gsi_state); 144 145 /* pc_sysfw.c */ 146 void x86_firmware_configure(void *ptr, int size); 147 148 #endif 149