1 /* 2 * Copyright (c) 2019 Red Hat, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2 or later, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT 9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 11 * more details. 12 * 13 * You should have received a copy of the GNU General Public License along with 14 * this program. If not, see <http://www.gnu.org/licenses/>. 15 */ 16 17 #ifndef HW_I386_X86_H 18 #define HW_I386_X86_H 19 20 #include "exec/hwaddr.h" 21 #include "qemu/notify.h" 22 23 #include "hw/boards.h" 24 #include "hw/nmi.h" 25 #include "hw/intc/ioapic.h" 26 #include "hw/isa/isa.h" 27 #include "qom/object.h" 28 29 struct X86MachineClass { 30 /*< private >*/ 31 MachineClass parent; 32 33 /*< public >*/ 34 35 /* TSC rate migration: */ 36 bool save_tsc_khz; 37 /* use DMA capable linuxboot option rom */ 38 bool fwcfg_dma_enabled; 39 }; 40 41 struct X86MachineState { 42 /*< private >*/ 43 MachineState parent; 44 45 /*< public >*/ 46 47 /* Pointers to devices and objects: */ 48 ISADevice *rtc; 49 FWCfgState *fw_cfg; 50 qemu_irq *gsi; 51 DeviceState *ioapic2; 52 GMappedFile *initrd_mapped_file; 53 HotplugHandler *acpi_dev; 54 55 /* RAM information (sizes, addresses, configuration): */ 56 ram_addr_t below_4g_mem_size, above_4g_mem_size; 57 58 /* Start address of the initial RAM above 4G */ 59 uint64_t above_4g_mem_start; 60 61 /* CPU and apic information: */ 62 bool apic_xrupt_override; 63 unsigned pci_irq_mask; 64 unsigned apic_id_limit; 65 uint16_t boot_cpus; 66 SgxEPCList *sgx_epc_list; 67 68 OnOffAuto smm; 69 OnOffAuto acpi; 70 OnOffAuto pit; 71 OnOffAuto pic; 72 73 char *oem_id; 74 char *oem_table_id; 75 /* 76 * Address space used by IOAPIC device. All IOAPIC interrupts 77 * will be translated to MSI messages in the address space. 78 */ 79 AddressSpace *ioapic_as; 80 81 /* 82 * Ratelimit enforced on detected bus locks in guest. 83 * The default value of the bus_lock_ratelimit is 0 per second, 84 * which means no limitation on the guest's bus locks. 85 */ 86 uint64_t bus_lock_ratelimit; 87 }; 88 89 #define X86_MACHINE_SMM "smm" 90 #define X86_MACHINE_ACPI "acpi" 91 #define X86_MACHINE_PIT "pit" 92 #define X86_MACHINE_PIC "pic" 93 #define X86_MACHINE_OEM_ID "x-oem-id" 94 #define X86_MACHINE_OEM_TABLE_ID "x-oem-table-id" 95 #define X86_MACHINE_BUS_LOCK_RATELIMIT "bus-lock-ratelimit" 96 97 #define TYPE_X86_MACHINE MACHINE_TYPE_NAME("x86") 98 OBJECT_DECLARE_TYPE(X86MachineState, X86MachineClass, X86_MACHINE) 99 100 uint32_t x86_cpu_apic_id_from_index(X86MachineState *pcms, 101 unsigned int cpu_index); 102 103 void x86_cpu_new(X86MachineState *pcms, int64_t apic_id, Error **errp); 104 void x86_cpus_init(X86MachineState *pcms, int default_cpu_version); 105 CpuInstanceProperties x86_cpu_index_to_props(MachineState *ms, 106 unsigned cpu_index); 107 int64_t x86_get_default_cpu_node_id(const MachineState *ms, int idx); 108 const CPUArchIdList *x86_possible_cpu_arch_ids(MachineState *ms); 109 CPUArchId *x86_find_cpu_slot(MachineState *ms, uint32_t id, int *idx); 110 void x86_rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count); 111 void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, 112 DeviceState *dev, Error **errp); 113 void x86_cpu_plug(HotplugHandler *hotplug_dev, 114 DeviceState *dev, Error **errp); 115 void x86_cpu_unplug_request_cb(HotplugHandler *hotplug_dev, 116 DeviceState *dev, Error **errp); 117 void x86_cpu_unplug_cb(HotplugHandler *hotplug_dev, 118 DeviceState *dev, Error **errp); 119 120 void x86_bios_rom_init(MachineState *ms, const char *default_firmware, 121 MemoryRegion *rom_memory, bool isapc_ram_fw); 122 123 void x86_load_linux(X86MachineState *x86ms, 124 FWCfgState *fw_cfg, 125 int acpi_data_size, 126 bool pvh_enabled); 127 128 bool x86_machine_is_smm_enabled(const X86MachineState *x86ms); 129 bool x86_machine_is_acpi_enabled(const X86MachineState *x86ms); 130 131 /* Global System Interrupts */ 132 133 #define ACPI_BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11)) 134 135 typedef struct GSIState { 136 qemu_irq i8259_irq[ISA_NUM_IRQS]; 137 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 138 qemu_irq ioapic2_irq[IOAPIC_NUM_PINS]; 139 } GSIState; 140 141 qemu_irq x86_allocate_cpu_irq(void); 142 void gsi_handler(void *opaque, int n, int level); 143 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 144 DeviceState *ioapic_init_secondary(GSIState *gsi_state); 145 146 /* pc_sysfw.c */ 147 void x86_firmware_configure(void *ptr, int size); 148 149 #endif 150