xref: /openbmc/qemu/include/hw/i386/x86-iommu.h (revision a68694cd)
1 /*
2  * Common IOMMU interface for X86 platform
3  *
4  * Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10 
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15 
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef HW_I386_X86_IOMMU_H
21 #define HW_I386_X86_IOMMU_H
22 
23 #include "hw/sysbus.h"
24 #include "hw/pci/pci.h"
25 #include "hw/pci/msi.h"
26 #include "qom/object.h"
27 
28 #define  TYPE_X86_IOMMU_DEVICE  ("x86-iommu")
29 typedef struct X86IOMMUClass X86IOMMUClass;
30 typedef struct X86IOMMUState X86IOMMUState;
31 DECLARE_OBJ_CHECKERS(X86IOMMUState, X86IOMMUClass,
32                      X86_IOMMU_DEVICE, TYPE_X86_IOMMU_DEVICE)
33 
34 #define X86_IOMMU_SID_INVALID             (0xffff)
35 
36 typedef struct X86IOMMUIrq X86IOMMUIrq;
37 typedef struct X86IOMMU_MSIMessage X86IOMMU_MSIMessage;
38 
39 typedef enum IommuType {
40     TYPE_INTEL,
41     TYPE_AMD,
42     TYPE_NONE
43 } IommuType;
44 
45 struct X86IOMMUClass {
46     SysBusDeviceClass parent;
47     /* Intel/AMD specific realize() hook */
48     DeviceRealize realize;
49     /* MSI-based interrupt remapping */
50     int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src,
51                      MSIMessage *dst, uint16_t sid);
52 };
53 
54 /**
55  * iec_notify_fn - IEC (Interrupt Entry Cache) notifier hook,
56  *                 triggered when IR invalidation happens.
57  * @private: private data
58  * @global: whether this is a global IEC invalidation
59  * @index: IRTE index to invalidate (start from)
60  * @mask: invalidation mask
61  */
62 typedef void (*iec_notify_fn)(void *private, bool global,
63                               uint32_t index, uint32_t mask);
64 
65 struct IEC_Notifier {
66     iec_notify_fn iec_notify;
67     void *private;
68     QLIST_ENTRY(IEC_Notifier) list;
69 };
70 typedef struct IEC_Notifier IEC_Notifier;
71 
72 struct X86IOMMUState {
73     SysBusDevice busdev;
74     OnOffAuto intr_supported;   /* Whether vIOMMU supports IR */
75     bool dt_supported;          /* Whether vIOMMU supports DT */
76     bool pt_supported;          /* Whether vIOMMU supports pass-through */
77     IommuType type;             /* IOMMU type - AMD/Intel     */
78     QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */
79 };
80 
81 bool x86_iommu_ir_supported(X86IOMMUState *s);
82 
83 /* Generic IRQ entry information when interrupt remapping is enabled */
84 struct X86IOMMUIrq {
85     /* Used by both IOAPIC/MSI interrupt remapping */
86     uint8_t trigger_mode;
87     uint8_t vector;
88     uint8_t delivery_mode;
89     uint32_t dest;
90     uint8_t dest_mode;
91 
92     /* only used by MSI interrupt remapping */
93     uint8_t redir_hint;
94     uint8_t msi_addr_last_bits;
95 };
96 
97 struct X86IOMMU_MSIMessage {
98     union {
99         struct {
100 #ifdef HOST_WORDS_BIGENDIAN
101             uint32_t __addr_head:12; /* 0xfee */
102             uint32_t dest:8;
103             uint32_t __reserved:8;
104             uint32_t redir_hint:1;
105             uint32_t dest_mode:1;
106             uint32_t __not_used:2;
107 #else
108             uint32_t __not_used:2;
109             uint32_t dest_mode:1;
110             uint32_t redir_hint:1;
111             uint32_t __reserved:8;
112             uint32_t dest:8;
113             uint32_t __addr_head:12; /* 0xfee */
114 #endif
115             uint32_t __addr_hi;
116         } QEMU_PACKED;
117         uint64_t msi_addr;
118     };
119     union {
120         struct {
121 #ifdef HOST_WORDS_BIGENDIAN
122             uint16_t trigger_mode:1;
123             uint16_t level:1;
124             uint16_t __resved:3;
125             uint16_t delivery_mode:3;
126             uint16_t vector:8;
127 #else
128             uint16_t vector:8;
129             uint16_t delivery_mode:3;
130             uint16_t __resved:3;
131             uint16_t level:1;
132             uint16_t trigger_mode:1;
133 #endif
134             uint16_t __resved1;
135         } QEMU_PACKED;
136         uint32_t msi_data;
137     };
138 };
139 
140 /**
141  * x86_iommu_get_default - get default IOMMU device
142  * @return: pointer to default IOMMU device
143  */
144 X86IOMMUState *x86_iommu_get_default(void);
145 
146 /*
147  * x86_iommu_get_type - get IOMMU type
148  */
149 IommuType x86_iommu_get_type(void);
150 
151 /**
152  * x86_iommu_iec_register_notifier - register IEC (Interrupt Entry
153  *                                   Cache) notifiers
154  * @iommu: IOMMU device to register
155  * @fn: IEC notifier hook function
156  * @data: notifier private data
157  */
158 void x86_iommu_iec_register_notifier(X86IOMMUState *iommu,
159                                      iec_notify_fn fn, void *data);
160 
161 /**
162  * x86_iommu_iec_notify_all - Notify IEC invalidations
163  * @iommu: IOMMU device that sends the notification
164  * @global: whether this is a global invalidation. If true, @index
165  *          and @mask are undefined.
166  * @index: starting index of interrupt entry to invalidate
167  * @mask: index mask for the invalidation
168  */
169 void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
170                               uint32_t index, uint32_t mask);
171 
172 /**
173  * x86_iommu_irq_to_msi_message - Populate one MSIMessage from X86IOMMUIrq
174  * @X86IOMMUIrq: The IRQ information
175  * @out: Output MSI message
176  */
177 void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *out);
178 #endif
179