xref: /openbmc/qemu/include/hw/i386/x86-iommu.h (revision 19ac7b29)
1 /*
2  * Common IOMMU interface for X86 platform
3  *
4  * Copyright (C) 2016 Peter Xu, Red Hat <peterx@redhat.com>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10 
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15 
16  * You should have received a copy of the GNU General Public License along
17  * with this program; if not, see <http://www.gnu.org/licenses/>.
18  */
19 
20 #ifndef HW_I386_X86_IOMMU_H
21 #define HW_I386_X86_IOMMU_H
22 
23 #include "hw/sysbus.h"
24 #include "hw/pci/msi.h"
25 #include "qom/object.h"
26 
27 #define  TYPE_X86_IOMMU_DEVICE  ("x86-iommu")
28 OBJECT_DECLARE_TYPE(X86IOMMUState, X86IOMMUClass, X86_IOMMU_DEVICE)
29 
30 #define X86_IOMMU_SID_INVALID             (0xffff)
31 
32 typedef struct X86IOMMUIrq X86IOMMUIrq;
33 typedef struct X86IOMMU_MSIMessage X86IOMMU_MSIMessage;
34 
35 struct X86IOMMUClass {
36     SysBusDeviceClass parent;
37     /* Intel/AMD specific realize() hook */
38     DeviceRealize realize;
39     /* MSI-based interrupt remapping */
40     int (*int_remap)(X86IOMMUState *iommu, MSIMessage *src,
41                      MSIMessage *dst, uint16_t sid);
42 };
43 
44 /**
45  * iec_notify_fn - IEC (Interrupt Entry Cache) notifier hook,
46  *                 triggered when IR invalidation happens.
47  * @private: private data
48  * @global: whether this is a global IEC invalidation
49  * @index: IRTE index to invalidate (start from)
50  * @mask: invalidation mask
51  */
52 typedef void (*iec_notify_fn)(void *private, bool global,
53                               uint32_t index, uint32_t mask);
54 
55 struct IEC_Notifier {
56     iec_notify_fn iec_notify;
57     void *private;
58     QLIST_ENTRY(IEC_Notifier) list;
59 };
60 typedef struct IEC_Notifier IEC_Notifier;
61 
62 struct X86IOMMUState {
63     SysBusDevice busdev;
64     OnOffAuto intr_supported;   /* Whether vIOMMU supports IR */
65     bool dt_supported;          /* Whether vIOMMU supports DT */
66     bool pt_supported;          /* Whether vIOMMU supports pass-through */
67     QLIST_HEAD(, IEC_Notifier) iec_notifiers; /* IEC notify list */
68 };
69 
70 bool x86_iommu_ir_supported(X86IOMMUState *s);
71 
72 /* Generic IRQ entry information when interrupt remapping is enabled */
73 struct X86IOMMUIrq {
74     /* Used by both IOAPIC/MSI interrupt remapping */
75     uint8_t trigger_mode;
76     uint8_t vector;
77     uint8_t delivery_mode;
78     uint32_t dest;
79     uint8_t dest_mode;
80 
81     /* only used by MSI interrupt remapping */
82     uint8_t redir_hint;
83     uint8_t msi_addr_last_bits;
84 };
85 
86 struct X86IOMMU_MSIMessage {
87     union {
88         struct {
89 #if HOST_BIG_ENDIAN
90             uint64_t __addr_hi:32;
91             uint64_t __addr_head:12; /* 0xfee */
92             uint64_t dest:8;
93             uint64_t __reserved:8;
94             uint64_t redir_hint:1;
95             uint64_t dest_mode:1;
96             uint64_t __not_used:2;
97 #else
98             uint64_t __not_used:2;
99             uint64_t dest_mode:1;
100             uint64_t redir_hint:1;
101             uint64_t __reserved:8;
102             uint64_t dest:8;
103             uint64_t __addr_head:12; /* 0xfee */
104             uint64_t __addr_hi:32;
105 #endif
106         } QEMU_PACKED;
107         uint64_t msi_addr;
108     };
109     union {
110         struct {
111 #if HOST_BIG_ENDIAN
112             uint32_t __resved1:16;
113             uint32_t trigger_mode:1;
114             uint32_t level:1;
115             uint32_t __resved:3;
116             uint32_t delivery_mode:3;
117             uint32_t vector:8;
118 #else
119             uint32_t vector:8;
120             uint32_t delivery_mode:3;
121             uint32_t __resved:3;
122             uint32_t level:1;
123             uint32_t trigger_mode:1;
124             uint32_t __resved1:16;
125 #endif
126         } QEMU_PACKED;
127         uint32_t msi_data;
128     };
129 };
130 
131 /**
132  * x86_iommu_get_default - get default IOMMU device
133  * @return: pointer to default IOMMU device
134  */
135 X86IOMMUState *x86_iommu_get_default(void);
136 
137 /**
138  * x86_iommu_iec_register_notifier - register IEC (Interrupt Entry
139  *                                   Cache) notifiers
140  * @iommu: IOMMU device to register
141  * @fn: IEC notifier hook function
142  * @data: notifier private data
143  */
144 void x86_iommu_iec_register_notifier(X86IOMMUState *iommu,
145                                      iec_notify_fn fn, void *data);
146 
147 /**
148  * x86_iommu_iec_notify_all - Notify IEC invalidations
149  * @iommu: IOMMU device that sends the notification
150  * @global: whether this is a global invalidation. If true, @index
151  *          and @mask are undefined.
152  * @index: starting index of interrupt entry to invalidate
153  * @mask: index mask for the invalidation
154  */
155 void x86_iommu_iec_notify_all(X86IOMMUState *iommu, bool global,
156                               uint32_t index, uint32_t mask);
157 
158 /**
159  * x86_iommu_irq_to_msi_message - Populate one MSIMessage from X86IOMMUIrq
160  * @X86IOMMUIrq: The IRQ information
161  * @out: Output MSI message
162  */
163 void x86_iommu_irq_to_msi_message(X86IOMMUIrq *irq, MSIMessage *out);
164 #endif
165