1 /* 2 * x86 CPU topology data structures and functions 3 * 4 * Copyright (c) 2012 Red Hat Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 #ifndef HW_I386_TOPOLOGY_H 25 #define HW_I386_TOPOLOGY_H 26 27 /* 28 * This file implements the APIC-ID-based CPU topology enumeration logic, 29 * documented at the following document: 30 * Intel® 64 Architecture Processor Topology Enumeration 31 * http://software.intel.com/en-us/articles/intel-64-architecture-processor-topology-enumeration/ 32 * 33 * This code should be compatible with AMD's "Extended Method" described at: 34 * AMD CPUID Specification (Publication #25481) 35 * Section 3: Multiple Core Calculation 36 * as long as: 37 * nr_threads is set to 1; 38 * OFFSET_IDX is assumed to be 0; 39 * CPUID Fn8000_0008_ECX[ApicIdCoreIdSize[3:0]] is set to apicid_core_width(). 40 */ 41 42 43 #include "qemu/bitops.h" 44 45 /* 46 * APIC IDs can be 32-bit, but beware: APIC IDs > 255 require x2APIC support 47 */ 48 typedef uint32_t apic_id_t; 49 50 typedef struct X86CPUTopoIDs { 51 unsigned pkg_id; 52 unsigned die_id; 53 unsigned module_id; 54 unsigned core_id; 55 unsigned smt_id; 56 } X86CPUTopoIDs; 57 58 typedef struct X86CPUTopoInfo { 59 unsigned dies_per_pkg; 60 unsigned modules_per_die; 61 unsigned cores_per_module; 62 unsigned threads_per_core; 63 } X86CPUTopoInfo; 64 65 /* 66 * CPUTopoLevel is the general i386 topology hierarchical representation, 67 * ordered by increasing hierarchical relationship. 68 * Its enumeration value is not bound to the type value of Intel (CPUID[0x1F]) 69 * or AMD (CPUID[0x80000026]). 70 */ 71 enum CPUTopoLevel { 72 CPU_TOPO_LEVEL_INVALID, 73 CPU_TOPO_LEVEL_SMT, 74 CPU_TOPO_LEVEL_CORE, 75 CPU_TOPO_LEVEL_MODULE, 76 CPU_TOPO_LEVEL_DIE, 77 CPU_TOPO_LEVEL_PACKAGE, 78 CPU_TOPO_LEVEL_MAX, 79 }; 80 81 /* Return the bit width needed for 'count' IDs */ 82 static unsigned apicid_bitwidth_for_count(unsigned count) 83 { 84 g_assert(count >= 1); 85 count -= 1; 86 return count ? 32 - clz32(count) : 0; 87 } 88 89 /* Bit width of the SMT_ID (thread ID) field on the APIC ID */ 90 static inline unsigned apicid_smt_width(X86CPUTopoInfo *topo_info) 91 { 92 return apicid_bitwidth_for_count(topo_info->threads_per_core); 93 } 94 95 /* Bit width of the Core_ID field */ 96 static inline unsigned apicid_core_width(X86CPUTopoInfo *topo_info) 97 { 98 return apicid_bitwidth_for_count(topo_info->cores_per_module); 99 } 100 101 /* Bit width of the Module_ID field */ 102 static inline unsigned apicid_module_width(X86CPUTopoInfo *topo_info) 103 { 104 return apicid_bitwidth_for_count(topo_info->modules_per_die); 105 } 106 107 /* Bit width of the Die_ID field */ 108 static inline unsigned apicid_die_width(X86CPUTopoInfo *topo_info) 109 { 110 return apicid_bitwidth_for_count(topo_info->dies_per_pkg); 111 } 112 113 /* Bit offset of the Core_ID field */ 114 static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) 115 { 116 return apicid_smt_width(topo_info); 117 } 118 119 /* Bit offset of the Module_ID field */ 120 static inline unsigned apicid_module_offset(X86CPUTopoInfo *topo_info) 121 { 122 return apicid_core_offset(topo_info) + apicid_core_width(topo_info); 123 } 124 125 /* Bit offset of the Die_ID field */ 126 static inline unsigned apicid_die_offset(X86CPUTopoInfo *topo_info) 127 { 128 return apicid_module_offset(topo_info) + apicid_module_width(topo_info); 129 } 130 131 /* Bit offset of the Pkg_ID (socket ID) field */ 132 static inline unsigned apicid_pkg_offset(X86CPUTopoInfo *topo_info) 133 { 134 return apicid_die_offset(topo_info) + apicid_die_width(topo_info); 135 } 136 137 /* 138 * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID 139 * 140 * The caller must make sure core_id < nr_cores and smt_id < nr_threads. 141 */ 142 static inline apic_id_t x86_apicid_from_topo_ids(X86CPUTopoInfo *topo_info, 143 const X86CPUTopoIDs *topo_ids) 144 { 145 return (topo_ids->pkg_id << apicid_pkg_offset(topo_info)) | 146 (topo_ids->die_id << apicid_die_offset(topo_info)) | 147 (topo_ids->module_id << apicid_module_offset(topo_info)) | 148 (topo_ids->core_id << apicid_core_offset(topo_info)) | 149 topo_ids->smt_id; 150 } 151 152 /* 153 * Calculate thread/core/package IDs for a specific topology, 154 * based on (contiguous) CPU index 155 */ 156 static inline void x86_topo_ids_from_idx(X86CPUTopoInfo *topo_info, 157 unsigned cpu_index, 158 X86CPUTopoIDs *topo_ids) 159 { 160 unsigned nr_dies = topo_info->dies_per_pkg; 161 unsigned nr_modules = topo_info->modules_per_die; 162 unsigned nr_cores = topo_info->cores_per_module; 163 unsigned nr_threads = topo_info->threads_per_core; 164 165 topo_ids->pkg_id = cpu_index / (nr_dies * nr_modules * 166 nr_cores * nr_threads); 167 topo_ids->die_id = cpu_index / (nr_modules * nr_cores * 168 nr_threads) % nr_dies; 169 topo_ids->module_id = cpu_index / (nr_cores * nr_threads) % 170 nr_modules; 171 topo_ids->core_id = cpu_index / nr_threads % nr_cores; 172 topo_ids->smt_id = cpu_index % nr_threads; 173 } 174 175 /* 176 * Calculate thread/core/package IDs for a specific topology, 177 * based on APIC ID 178 */ 179 static inline void x86_topo_ids_from_apicid(apic_id_t apicid, 180 X86CPUTopoInfo *topo_info, 181 X86CPUTopoIDs *topo_ids) 182 { 183 topo_ids->smt_id = apicid & 184 ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); 185 topo_ids->core_id = 186 (apicid >> apicid_core_offset(topo_info)) & 187 ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); 188 topo_ids->module_id = 189 (apicid >> apicid_module_offset(topo_info)) & 190 ~(0xFFFFFFFFUL << apicid_module_width(topo_info)); 191 topo_ids->die_id = 192 (apicid >> apicid_die_offset(topo_info)) & 193 ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); 194 topo_ids->pkg_id = apicid >> apicid_pkg_offset(topo_info); 195 } 196 197 /* 198 * Make APIC ID for the CPU 'cpu_index' 199 * 200 * 'cpu_index' is a sequential, contiguous ID for the CPU. 201 */ 202 static inline apic_id_t x86_apicid_from_cpu_idx(X86CPUTopoInfo *topo_info, 203 unsigned cpu_index) 204 { 205 X86CPUTopoIDs topo_ids; 206 x86_topo_ids_from_idx(topo_info, cpu_index, &topo_ids); 207 return x86_apicid_from_topo_ids(topo_info, &topo_ids); 208 } 209 210 /* 211 * Check whether there's extended topology level (module or die)? 212 */ 213 static inline bool x86_has_extended_topo(unsigned long *topo_bitmap) 214 { 215 return test_bit(CPU_TOPO_LEVEL_MODULE, topo_bitmap) || 216 test_bit(CPU_TOPO_LEVEL_DIE, topo_bitmap); 217 } 218 219 #endif /* HW_I386_TOPOLOGY_H */ 220