1 /* 2 * SGX EPC device 3 * 4 * Copyright (C) 2019 Intel Corporation 5 * 6 * Authors: 7 * Sean Christopherson <sean.j.christopherson@intel.com> 8 * 9 * This work is licensed under the terms of the GNU GPL, version 2 or later. 10 * See the COPYING file in the top-level directory. 11 */ 12 #ifndef QEMU_SGX_EPC_H 13 #define QEMU_SGX_EPC_H 14 15 #include "hw/qdev-core.h" 16 #include "hw/i386/hostmem-epc.h" 17 18 #define TYPE_SGX_EPC "sgx-epc" 19 #define SGX_EPC(obj) \ 20 OBJECT_CHECK(SGXEPCDevice, (obj), TYPE_SGX_EPC) 21 #define SGX_EPC_CLASS(oc) \ 22 OBJECT_CLASS_CHECK(SGXEPCDeviceClass, (oc), TYPE_SGX_EPC) 23 #define SGX_EPC_GET_CLASS(obj) \ 24 OBJECT_GET_CLASS(SGXEPCDeviceClass, (obj), TYPE_SGX_EPC) 25 26 #define SGX_EPC_ADDR_PROP "addr" 27 #define SGX_EPC_SIZE_PROP "size" 28 #define SGX_EPC_MEMDEV_PROP "memdev" 29 #define SGX_EPC_NUMA_NODE_PROP "node" 30 31 /** 32 * SGXEPCDevice: 33 * @addr: starting guest physical address, where @SGXEPCDevice is mapped. 34 * Default value: 0, means that address is auto-allocated. 35 * @hostmem: host memory backend providing memory for @SGXEPCDevice 36 */ 37 typedef struct SGXEPCDevice { 38 /* private */ 39 DeviceState parent_obj; 40 41 /* public */ 42 uint64_t addr; 43 uint32_t node; 44 HostMemoryBackendEpc *hostmem; 45 } SGXEPCDevice; 46 47 /* 48 * @base: address in guest physical address space where EPC regions start 49 * @mr: address space container for memory devices 50 */ 51 typedef struct SGXEPCState { 52 uint64_t base; 53 uint64_t size; 54 55 MemoryRegion mr; 56 57 struct SGXEPCDevice **sections; 58 int nr_sections; 59 } SGXEPCState; 60 61 bool check_sgx_support(void); 62 bool sgx_epc_get_section(int section_nr, uint64_t *addr, uint64_t *size); 63 void sgx_epc_build_srat(GArray *table_data); 64 65 static inline uint64_t sgx_epc_above_4g_end(SGXEPCState *sgx_epc) 66 { 67 assert(sgx_epc != NULL && sgx_epc->base >= 0x100000000ULL); 68 69 return sgx_epc->base + sgx_epc->size; 70 } 71 72 #endif 73