1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu-common.h" 5 #include "exec/memory.h" 6 #include "hw/boards.h" 7 #include "hw/isa/isa.h" 8 #include "hw/block/fdc.h" 9 #include "net/net.h" 10 #include "hw/i386/ioapic.h" 11 12 #include "qemu/range.h" 13 #include "qemu/bitmap.h" 14 #include "sysemu/sysemu.h" 15 #include "hw/pci/pci.h" 16 #include "hw/mem/pc-dimm.h" 17 #include "hw/mem/nvdimm.h" 18 #include "hw/acpi/acpi_dev_interface.h" 19 20 #define HPET_INTCAP "hpet-intcap" 21 22 /** 23 * PCMachineState: 24 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 25 * @boot_cpus: number of present VCPUs 26 */ 27 struct PCMachineState { 28 /*< private >*/ 29 MachineState parent_obj; 30 31 /* <public> */ 32 33 /* State for other subsystems/APIs: */ 34 Notifier machine_done; 35 36 /* Pointers to devices and objects: */ 37 HotplugHandler *acpi_dev; 38 ISADevice *rtc; 39 PCIBus *bus; 40 FWCfgState *fw_cfg; 41 qemu_irq *gsi; 42 43 /* Configuration options: */ 44 uint64_t max_ram_below_4g; 45 OnOffAuto vmport; 46 OnOffAuto smm; 47 48 bool acpi_build_enabled; 49 bool smbus_enabled; 50 bool sata_enabled; 51 bool pit_enabled; 52 53 /* RAM information (sizes, addresses, configuration): */ 54 ram_addr_t below_4g_mem_size, above_4g_mem_size; 55 56 /* CPU and apic information: */ 57 bool apic_xrupt_override; 58 unsigned apic_id_limit; 59 uint16_t boot_cpus; 60 61 /* NUMA information: */ 62 uint64_t numa_nodes; 63 uint64_t *node_mem; 64 65 /* Address space used by IOAPIC device. All IOAPIC interrupts 66 * will be translated to MSI messages in the address space. */ 67 AddressSpace *ioapic_as; 68 }; 69 70 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 71 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" 72 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 73 #define PC_MACHINE_VMPORT "vmport" 74 #define PC_MACHINE_SMM "smm" 75 #define PC_MACHINE_SMBUS "smbus" 76 #define PC_MACHINE_SATA "sata" 77 #define PC_MACHINE_PIT "pit" 78 79 /** 80 * PCMachineClass: 81 * 82 * Compat fields: 83 * 84 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 85 * backend's alignment value if provided 86 * @acpi_data_size: Size of the chunk of memory at the top of RAM 87 * for the BIOS ACPI tables and other BIOS 88 * datastructures. 89 * @gigabyte_align: Make sure that guest addresses aligned at 90 * 1Gbyte boundaries get mapped to host 91 * addresses aligned at 1Gbyte boundaries. This 92 * way we can use 1GByte pages in the host. 93 * 94 */ 95 typedef struct PCMachineClass { 96 /*< private >*/ 97 MachineClass parent_class; 98 99 /*< public >*/ 100 101 /* Device configuration: */ 102 bool pci_enabled; 103 bool kvmclock_enabled; 104 const char *default_nic_model; 105 106 /* Compat options: */ 107 108 /* ACPI compat: */ 109 bool has_acpi_build; 110 bool rsdp_in_ram; 111 int legacy_acpi_table_size; 112 unsigned acpi_data_size; 113 114 /* SMBIOS compat: */ 115 bool smbios_defaults; 116 bool smbios_legacy_mode; 117 bool smbios_uuid_encoded; 118 119 /* RAM / address space compat: */ 120 bool gigabyte_align; 121 bool has_reserved_memory; 122 bool enforce_aligned_dimm; 123 bool broken_reserved_end; 124 125 /* TSC rate migration: */ 126 bool save_tsc_khz; 127 /* generate legacy CPU hotplug AML */ 128 bool legacy_cpu_hotplug; 129 130 /* use DMA capable linuxboot option rom */ 131 bool linuxboot_dma_enabled; 132 133 /* use PVH to load kernels that support this feature */ 134 bool pvh_enabled; 135 } PCMachineClass; 136 137 #define TYPE_PC_MACHINE "generic-pc-machine" 138 #define PC_MACHINE(obj) \ 139 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE) 140 #define PC_MACHINE_GET_CLASS(obj) \ 141 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE) 142 #define PC_MACHINE_CLASS(klass) \ 143 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) 144 145 /* i8259.c */ 146 147 extern DeviceState *isa_pic; 148 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); 149 qemu_irq *kvm_i8259_init(ISABus *bus); 150 int pic_read_irq(DeviceState *d); 151 int pic_get_output(DeviceState *d); 152 153 /* ioapic.c */ 154 155 /* Global System Interrupts */ 156 157 #define GSI_NUM_PINS IOAPIC_NUM_PINS 158 159 typedef struct GSIState { 160 qemu_irq i8259_irq[ISA_NUM_IRQS]; 161 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 162 } GSIState; 163 164 void gsi_handler(void *opaque, int n, int level); 165 166 /* vmport.c */ 167 #define TYPE_VMPORT "vmport" 168 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); 169 170 static inline void vmport_init(ISABus *bus) 171 { 172 isa_create_simple(bus, TYPE_VMPORT); 173 } 174 175 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); 176 void vmmouse_get_data(uint32_t *data); 177 void vmmouse_set_data(const uint32_t *data); 178 179 /* pc.c */ 180 extern int fd_bootchk; 181 182 bool pc_machine_is_smm_enabled(PCMachineState *pcms); 183 void pc_register_ferr_irq(qemu_irq irq); 184 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 185 186 void pc_cpus_init(PCMachineState *pcms); 187 void pc_hot_add_cpu(const int64_t id, Error **errp); 188 189 void pc_guest_info_init(PCMachineState *pcms); 190 191 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 192 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 193 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 194 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 195 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 196 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 197 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 198 199 200 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 201 MemoryRegion *pci_address_space); 202 203 void xen_load_linux(PCMachineState *pcms); 204 void pc_memory_init(PCMachineState *pcms, 205 MemoryRegion *system_memory, 206 MemoryRegion *rom_memory, 207 MemoryRegion **ram_memory); 208 uint64_t pc_pci_hole64_start(void); 209 qemu_irq pc_allocate_cpu_irq(void); 210 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 211 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 212 ISADevice **rtc_state, 213 bool create_fdctrl, 214 bool no_vmport, 215 bool has_pit, 216 uint32_t hpet_irqs); 217 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 218 void pc_cmos_init(PCMachineState *pcms, 219 BusState *ide0, BusState *ide1, 220 ISADevice *s); 221 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 222 void pc_pci_device_init(PCIBus *pci_bus); 223 224 typedef void (*cpu_set_smm_t)(int smm, void *arg); 225 226 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 227 228 ISADevice *pc_find_fdc0(void); 229 int cmos_get_fd_drive_type(FloppyDriveType fd0); 230 231 #define FW_CFG_IO_BASE 0x510 232 233 #define PORT92_A20_LINE "a20" 234 235 /* acpi_piix.c */ 236 237 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 238 qemu_irq sci_irq, qemu_irq smi_irq, 239 int smm_enabled, DeviceState **piix4_pm); 240 241 /* hpet.c */ 242 extern int no_hpet; 243 244 /* piix_pci.c */ 245 struct PCII440FXState; 246 typedef struct PCII440FXState PCII440FXState; 247 248 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" 249 #define TYPE_I440FX_PCI_DEVICE "i440FX" 250 251 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" 252 253 /* 254 * Reset Control Register: PCI-accessible ISA-Compatible Register at address 255 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 256 */ 257 #define RCR_IOPORT 0xcf9 258 259 PCIBus *i440fx_init(const char *host_type, const char *pci_type, 260 PCII440FXState **pi440fx_state, int *piix_devfn, 261 ISABus **isa_bus, qemu_irq *pic, 262 MemoryRegion *address_space_mem, 263 MemoryRegion *address_space_io, 264 ram_addr_t ram_size, 265 ram_addr_t below_4g_mem_size, 266 ram_addr_t above_4g_mem_size, 267 MemoryRegion *pci_memory, 268 MemoryRegion *ram_memory); 269 270 PCIBus *find_i440fx(void); 271 /* piix4.c */ 272 extern PCIDevice *piix4_dev; 273 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); 274 275 /* pc_sysfw.c */ 276 void pc_system_firmware_init(MemoryRegion *rom_memory, 277 bool isapc_ram_fw); 278 279 /* acpi-build.c */ 280 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 281 const CPUArchIdList *apic_ids, GArray *entry); 282 283 /* e820 types */ 284 #define E820_RAM 1 285 #define E820_RESERVED 2 286 #define E820_ACPI 3 287 #define E820_NVS 4 288 #define E820_UNUSABLE 5 289 290 int e820_add_entry(uint64_t, uint64_t, uint32_t); 291 int e820_get_num_entries(void); 292 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); 293 294 extern GlobalProperty pc_compat_3_1[]; 295 extern const size_t pc_compat_3_1_len; 296 297 extern GlobalProperty pc_compat_3_0[]; 298 extern const size_t pc_compat_3_0_len; 299 300 extern GlobalProperty pc_compat_2_12[]; 301 extern const size_t pc_compat_2_12_len; 302 303 extern GlobalProperty pc_compat_2_11[]; 304 extern const size_t pc_compat_2_11_len; 305 306 extern GlobalProperty pc_compat_2_10[]; 307 extern const size_t pc_compat_2_10_len; 308 309 extern GlobalProperty pc_compat_2_9[]; 310 extern const size_t pc_compat_2_9_len; 311 312 extern GlobalProperty pc_compat_2_8[]; 313 extern const size_t pc_compat_2_8_len; 314 315 extern GlobalProperty pc_compat_2_7[]; 316 extern const size_t pc_compat_2_7_len; 317 318 extern GlobalProperty pc_compat_2_6[]; 319 extern const size_t pc_compat_2_6_len; 320 321 extern GlobalProperty pc_compat_2_5[]; 322 extern const size_t pc_compat_2_5_len; 323 324 extern GlobalProperty pc_compat_2_4[]; 325 extern const size_t pc_compat_2_4_len; 326 327 extern GlobalProperty pc_compat_2_3[]; 328 extern const size_t pc_compat_2_3_len; 329 330 extern GlobalProperty pc_compat_2_2[]; 331 extern const size_t pc_compat_2_2_len; 332 333 extern GlobalProperty pc_compat_2_1[]; 334 extern const size_t pc_compat_2_1_len; 335 336 extern GlobalProperty pc_compat_2_0[]; 337 extern const size_t pc_compat_2_0_len; 338 339 extern GlobalProperty pc_compat_1_7[]; 340 extern const size_t pc_compat_1_7_len; 341 342 extern GlobalProperty pc_compat_1_6[]; 343 extern const size_t pc_compat_1_6_len; 344 345 extern GlobalProperty pc_compat_1_5[]; 346 extern const size_t pc_compat_1_5_len; 347 348 extern GlobalProperty pc_compat_1_4[]; 349 extern const size_t pc_compat_1_4_len; 350 351 /* Helper for setting model-id for CPU models that changed model-id 352 * depending on QEMU versions up to QEMU 2.4. 353 */ 354 #define PC_CPU_MODEL_IDS(v) \ 355 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 356 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 357 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 358 359 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 360 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 361 { \ 362 MachineClass *mc = MACHINE_CLASS(oc); \ 363 optsfn(mc); \ 364 mc->init = initfn; \ 365 } \ 366 static const TypeInfo pc_machine_type_##suffix = { \ 367 .name = namestr TYPE_MACHINE_SUFFIX, \ 368 .parent = TYPE_PC_MACHINE, \ 369 .class_init = pc_machine_##suffix##_class_init, \ 370 }; \ 371 static void pc_machine_init_##suffix(void) \ 372 { \ 373 type_register(&pc_machine_type_##suffix); \ 374 } \ 375 type_init(pc_machine_init_##suffix) 376 377 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); 378 #endif 379