1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu-common.h" 5 #include "exec/memory.h" 6 #include "hw/boards.h" 7 #include "hw/isa/isa.h" 8 #include "hw/block/fdc.h" 9 #include "net/net.h" 10 #include "hw/i386/ioapic.h" 11 12 #include "qemu/range.h" 13 #include "qemu/bitmap.h" 14 #include "sysemu/sysemu.h" 15 #include "hw/pci/pci.h" 16 #include "hw/boards.h" 17 #include "hw/compat.h" 18 #include "hw/mem/pc-dimm.h" 19 20 #define HPET_INTCAP "hpet-intcap" 21 22 /** 23 * PCMachineState: 24 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 25 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 26 * backend's alignment value if provided 27 */ 28 struct PCMachineState { 29 /*< private >*/ 30 MachineState parent_obj; 31 32 /* <public> */ 33 MemoryHotplugState hotplug_memory; 34 35 HotplugHandler *acpi_dev; 36 ISADevice *rtc; 37 38 uint64_t max_ram_below_4g; 39 OnOffAuto vmport; 40 OnOffAuto smm; 41 bool enforce_aligned_dimm; 42 }; 43 44 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 45 #define PC_MACHINE_MEMHP_REGION_SIZE "hotplug-memory-region-size" 46 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 47 #define PC_MACHINE_VMPORT "vmport" 48 #define PC_MACHINE_SMM "smm" 49 #define PC_MACHINE_ENFORCE_ALIGNED_DIMM "enforce-aligned-dimm" 50 51 /** 52 * PCMachineClass: 53 * @get_hotplug_handler: pointer to parent class callback @get_hotplug_handler 54 */ 55 struct PCMachineClass { 56 /*< private >*/ 57 MachineClass parent_class; 58 59 /*< public >*/ 60 HotplugHandler *(*get_hotplug_handler)(MachineState *machine, 61 DeviceState *dev); 62 }; 63 64 typedef struct PCMachineState PCMachineState; 65 typedef struct PCMachineClass PCMachineClass; 66 67 #define TYPE_PC_MACHINE "generic-pc-machine" 68 #define PC_MACHINE(obj) \ 69 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE) 70 #define PC_MACHINE_GET_CLASS(obj) \ 71 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE) 72 #define PC_MACHINE_CLASS(klass) \ 73 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) 74 75 /* PC-style peripherals (also used by other machines). */ 76 77 typedef struct PcPciInfo { 78 Range w32; 79 Range w64; 80 } PcPciInfo; 81 82 #define ACPI_PM_PROP_S3_DISABLED "disable_s3" 83 #define ACPI_PM_PROP_S4_DISABLED "disable_s4" 84 #define ACPI_PM_PROP_S4_VAL "s4_val" 85 #define ACPI_PM_PROP_SCI_INT "sci_int" 86 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd" 87 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd" 88 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base" 89 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk" 90 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" 91 #define ACPI_PM_PROP_TCO_ENABLED "enable_tco" 92 93 struct PcGuestInfo { 94 bool isapc_ram_fw; 95 hwaddr ram_size, ram_size_below_4g; 96 unsigned apic_id_limit; 97 bool apic_xrupt_override; 98 uint64_t numa_nodes; 99 uint64_t *node_mem; 100 uint64_t *node_cpu; 101 FWCfgState *fw_cfg; 102 int legacy_acpi_table_size; 103 bool has_acpi_build; 104 bool has_reserved_memory; 105 bool rsdp_in_ram; 106 }; 107 108 /* parallel.c */ 109 110 void parallel_hds_isa_init(ISABus *bus, int n); 111 112 bool parallel_mm_init(MemoryRegion *address_space, 113 hwaddr base, int it_shift, qemu_irq irq, 114 CharDriverState *chr); 115 116 /* i8259.c */ 117 118 extern DeviceState *isa_pic; 119 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); 120 qemu_irq *kvm_i8259_init(ISABus *bus); 121 int pic_read_irq(DeviceState *d); 122 int pic_get_output(DeviceState *d); 123 void hmp_info_pic(Monitor *mon, const QDict *qdict); 124 void hmp_info_irq(Monitor *mon, const QDict *qdict); 125 126 /* Global System Interrupts */ 127 128 #define GSI_NUM_PINS IOAPIC_NUM_PINS 129 130 typedef struct GSIState { 131 qemu_irq i8259_irq[ISA_NUM_IRQS]; 132 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 133 } GSIState; 134 135 void gsi_handler(void *opaque, int n, int level); 136 137 /* vmport.c */ 138 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); 139 140 static inline void vmport_init(ISABus *bus) 141 { 142 isa_create_simple(bus, "vmport"); 143 } 144 145 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); 146 void vmmouse_get_data(uint32_t *data); 147 void vmmouse_set_data(const uint32_t *data); 148 149 /* pckbd.c */ 150 151 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); 152 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 153 MemoryRegion *region, ram_addr_t size, 154 hwaddr mask); 155 void i8042_isa_mouse_fake_event(void *opaque); 156 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out); 157 158 /* pc.c */ 159 extern int fd_bootchk; 160 161 bool pc_machine_is_smm_enabled(PCMachineState *pcms); 162 void pc_register_ferr_irq(qemu_irq irq); 163 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 164 165 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge); 166 void pc_hot_add_cpu(const int64_t id, Error **errp); 167 void pc_acpi_init(const char *default_dsdt); 168 169 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 170 ram_addr_t above_4g_mem_size); 171 172 void pc_set_legacy_acpi_data_size(void); 173 174 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 175 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 176 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 177 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 178 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 179 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL) 180 181 182 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 183 MemoryRegion *pci_address_space); 184 185 FWCfgState *xen_load_linux(const char *kernel_filename, 186 const char *kernel_cmdline, 187 const char *initrd_filename, 188 ram_addr_t below_4g_mem_size, 189 PcGuestInfo *guest_info); 190 FWCfgState *pc_memory_init(MachineState *machine, 191 MemoryRegion *system_memory, 192 ram_addr_t below_4g_mem_size, 193 ram_addr_t above_4g_mem_size, 194 MemoryRegion *rom_memory, 195 MemoryRegion **ram_memory, 196 PcGuestInfo *guest_info); 197 qemu_irq pc_allocate_cpu_irq(void); 198 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 199 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 200 ISADevice **rtc_state, 201 bool create_fdctrl, 202 bool no_vmport, 203 uint32 hpet_irqs); 204 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 205 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 206 const char *boot_device, MachineState *machine, 207 BusState *ide0, BusState *ide1, 208 ISADevice *s); 209 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus); 210 void pc_pci_device_init(PCIBus *pci_bus); 211 212 typedef void (*cpu_set_smm_t)(int smm, void *arg); 213 214 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 215 216 /* acpi_piix.c */ 217 218 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 219 qemu_irq sci_irq, qemu_irq smi_irq, 220 int smm_enabled, DeviceState **piix4_pm); 221 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); 222 223 /* hpet.c */ 224 extern int no_hpet; 225 226 /* piix_pci.c */ 227 struct PCII440FXState; 228 typedef struct PCII440FXState PCII440FXState; 229 230 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, 231 ISABus **isa_bus, qemu_irq *pic, 232 MemoryRegion *address_space_mem, 233 MemoryRegion *address_space_io, 234 ram_addr_t ram_size, 235 ram_addr_t below_4g_mem_size, 236 ram_addr_t above_4g_mem_size, 237 MemoryRegion *pci_memory, 238 MemoryRegion *ram_memory); 239 240 PCIBus *find_i440fx(void); 241 /* piix4.c */ 242 extern PCIDevice *piix4_dev; 243 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); 244 245 /* vga.c */ 246 enum vga_retrace_method { 247 VGA_RETRACE_DUMB, 248 VGA_RETRACE_PRECISE 249 }; 250 251 extern enum vga_retrace_method vga_retrace_method; 252 253 int isa_vga_mm_init(hwaddr vram_base, 254 hwaddr ctrl_base, int it_shift, 255 MemoryRegion *address_space); 256 257 /* ne2000.c */ 258 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) 259 { 260 DeviceState *dev; 261 ISADevice *isadev; 262 263 qemu_check_nic_model(nd, "ne2k_isa"); 264 265 isadev = isa_try_create(bus, "ne2k_isa"); 266 if (!isadev) { 267 return false; 268 } 269 dev = DEVICE(isadev); 270 qdev_prop_set_uint32(dev, "iobase", base); 271 qdev_prop_set_uint32(dev, "irq", irq); 272 qdev_set_nic_properties(dev, nd); 273 qdev_init_nofail(dev); 274 return true; 275 } 276 277 /* pc_sysfw.c */ 278 void pc_system_firmware_init(MemoryRegion *rom_memory, 279 bool isapc_ram_fw); 280 281 /* pvpanic.c */ 282 uint16_t pvpanic_port(void); 283 284 /* e820 types */ 285 #define E820_RAM 1 286 #define E820_RESERVED 2 287 #define E820_ACPI 3 288 #define E820_NVS 4 289 #define E820_UNUSABLE 5 290 291 int e820_add_entry(uint64_t, uint64_t, uint32_t); 292 int e820_get_num_entries(void); 293 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); 294 295 #define PC_COMPAT_2_3 \ 296 HW_COMPAT_2_3 \ 297 {\ 298 .driver = TYPE_X86_CPU,\ 299 .property = "arat",\ 300 .value = "off",\ 301 },{\ 302 .driver = "qemu64" "-" TYPE_X86_CPU,\ 303 .property = "level",\ 304 .value = stringify(4),\ 305 },{\ 306 .driver = "kvm64" "-" TYPE_X86_CPU,\ 307 .property = "level",\ 308 .value = stringify(5),\ 309 },{\ 310 .driver = "pentium3" "-" TYPE_X86_CPU,\ 311 .property = "level",\ 312 .value = stringify(2),\ 313 },{\ 314 .driver = "n270" "-" TYPE_X86_CPU,\ 315 .property = "level",\ 316 .value = stringify(5),\ 317 },{\ 318 .driver = "Conroe" "-" TYPE_X86_CPU,\ 319 .property = "level",\ 320 .value = stringify(4),\ 321 },{\ 322 .driver = "Penryn" "-" TYPE_X86_CPU,\ 323 .property = "level",\ 324 .value = stringify(4),\ 325 },{\ 326 .driver = "Nehalem" "-" TYPE_X86_CPU,\ 327 .property = "level",\ 328 .value = stringify(4),\ 329 },{\ 330 .driver = "n270" "-" TYPE_X86_CPU,\ 331 .property = "xlevel",\ 332 .value = stringify(0x8000000a),\ 333 },{\ 334 .driver = "Penryn" "-" TYPE_X86_CPU,\ 335 .property = "xlevel",\ 336 .value = stringify(0x8000000a),\ 337 },{\ 338 .driver = "Conroe" "-" TYPE_X86_CPU,\ 339 .property = "xlevel",\ 340 .value = stringify(0x8000000a),\ 341 },{\ 342 .driver = "Nehalem" "-" TYPE_X86_CPU,\ 343 .property = "xlevel",\ 344 .value = stringify(0x8000000a),\ 345 },{\ 346 .driver = "Westmere" "-" TYPE_X86_CPU,\ 347 .property = "xlevel",\ 348 .value = stringify(0x8000000a),\ 349 },{\ 350 .driver = "SandyBridge" "-" TYPE_X86_CPU,\ 351 .property = "xlevel",\ 352 .value = stringify(0x8000000a),\ 353 },{\ 354 .driver = "IvyBridge" "-" TYPE_X86_CPU,\ 355 .property = "xlevel",\ 356 .value = stringify(0x8000000a),\ 357 },{\ 358 .driver = "Haswell" "-" TYPE_X86_CPU,\ 359 .property = "xlevel",\ 360 .value = stringify(0x8000000a),\ 361 },{\ 362 .driver = "Haswell-noTSX" "-" TYPE_X86_CPU,\ 363 .property = "xlevel",\ 364 .value = stringify(0x8000000a),\ 365 },{\ 366 .driver = "Broadwell" "-" TYPE_X86_CPU,\ 367 .property = "xlevel",\ 368 .value = stringify(0x8000000a),\ 369 },{\ 370 .driver = "Broadwell-noTSX" "-" TYPE_X86_CPU,\ 371 .property = "xlevel",\ 372 .value = stringify(0x8000000a),\ 373 }, 374 375 #define PC_COMPAT_2_2 \ 376 PC_COMPAT_2_3 \ 377 HW_COMPAT_2_2 378 379 #define PC_COMPAT_2_1 \ 380 PC_COMPAT_2_2 \ 381 HW_COMPAT_2_1 382 383 #define PC_COMPAT_2_0 \ 384 PC_COMPAT_2_1 \ 385 {\ 386 .driver = "virtio-scsi-pci",\ 387 .property = "any_layout",\ 388 .value = "off",\ 389 },{\ 390 .driver = "PIIX4_PM",\ 391 .property = "memory-hotplug-support",\ 392 .value = "off",\ 393 },\ 394 {\ 395 .driver = "apic",\ 396 .property = "version",\ 397 .value = stringify(0x11),\ 398 },\ 399 {\ 400 .driver = "nec-usb-xhci",\ 401 .property = "superspeed-ports-first",\ 402 .value = "off",\ 403 },\ 404 {\ 405 .driver = "nec-usb-xhci",\ 406 .property = "force-pcie-endcap",\ 407 .value = "on",\ 408 },\ 409 {\ 410 .driver = "pci-serial",\ 411 .property = "prog_if",\ 412 .value = stringify(0),\ 413 },\ 414 {\ 415 .driver = "pci-serial-2x",\ 416 .property = "prog_if",\ 417 .value = stringify(0),\ 418 },\ 419 {\ 420 .driver = "pci-serial-4x",\ 421 .property = "prog_if",\ 422 .value = stringify(0),\ 423 },\ 424 {\ 425 .driver = "virtio-net-pci",\ 426 .property = "guest_announce",\ 427 .value = "off",\ 428 },\ 429 {\ 430 .driver = "ICH9-LPC",\ 431 .property = "memory-hotplug-support",\ 432 .value = "off",\ 433 },{\ 434 .driver = "xio3130-downstream",\ 435 .property = COMPAT_PROP_PCP,\ 436 .value = "off",\ 437 },{\ 438 .driver = "ioh3420",\ 439 .property = COMPAT_PROP_PCP,\ 440 .value = "off",\ 441 }, 442 443 #define PC_COMPAT_1_7 \ 444 PC_COMPAT_2_0 \ 445 {\ 446 .driver = TYPE_USB_DEVICE,\ 447 .property = "msos-desc",\ 448 .value = "no",\ 449 },\ 450 {\ 451 .driver = "PIIX4_PM",\ 452 .property = "acpi-pci-hotplug-with-bridge-support",\ 453 .value = "off",\ 454 },\ 455 {\ 456 .driver = "hpet",\ 457 .property = HPET_INTCAP,\ 458 .value = stringify(4),\ 459 }, 460 461 #define PC_COMPAT_1_6 \ 462 PC_COMPAT_1_7 \ 463 {\ 464 .driver = "e1000",\ 465 .property = "mitigation",\ 466 .value = "off",\ 467 },{\ 468 .driver = "qemu64-" TYPE_X86_CPU,\ 469 .property = "model",\ 470 .value = stringify(2),\ 471 },{\ 472 .driver = "qemu32-" TYPE_X86_CPU,\ 473 .property = "model",\ 474 .value = stringify(3),\ 475 },{\ 476 .driver = "i440FX-pcihost",\ 477 .property = "short_root_bus",\ 478 .value = stringify(1),\ 479 },{\ 480 .driver = "q35-pcihost",\ 481 .property = "short_root_bus",\ 482 .value = stringify(1),\ 483 }, 484 485 #define PC_COMPAT_1_5 \ 486 PC_COMPAT_1_6 \ 487 {\ 488 .driver = "Conroe-" TYPE_X86_CPU,\ 489 .property = "model",\ 490 .value = stringify(2),\ 491 },{\ 492 .driver = "Conroe-" TYPE_X86_CPU,\ 493 .property = "level",\ 494 .value = stringify(2),\ 495 },{\ 496 .driver = "Penryn-" TYPE_X86_CPU,\ 497 .property = "model",\ 498 .value = stringify(2),\ 499 },{\ 500 .driver = "Penryn-" TYPE_X86_CPU,\ 501 .property = "level",\ 502 .value = stringify(2),\ 503 },{\ 504 .driver = "Nehalem-" TYPE_X86_CPU,\ 505 .property = "model",\ 506 .value = stringify(2),\ 507 },{\ 508 .driver = "Nehalem-" TYPE_X86_CPU,\ 509 .property = "level",\ 510 .value = stringify(2),\ 511 },{\ 512 .driver = "virtio-net-pci",\ 513 .property = "any_layout",\ 514 .value = "off",\ 515 },{\ 516 .driver = TYPE_X86_CPU,\ 517 .property = "pmu",\ 518 .value = "on",\ 519 },{\ 520 .driver = "i440FX-pcihost",\ 521 .property = "short_root_bus",\ 522 .value = stringify(0),\ 523 },{\ 524 .driver = "q35-pcihost",\ 525 .property = "short_root_bus",\ 526 .value = stringify(0),\ 527 }, 528 529 #define PC_COMPAT_1_4 \ 530 PC_COMPAT_1_5 \ 531 {\ 532 .driver = "scsi-hd",\ 533 .property = "discard_granularity",\ 534 .value = stringify(0),\ 535 },{\ 536 .driver = "scsi-cd",\ 537 .property = "discard_granularity",\ 538 .value = stringify(0),\ 539 },{\ 540 .driver = "scsi-disk",\ 541 .property = "discard_granularity",\ 542 .value = stringify(0),\ 543 },{\ 544 .driver = "ide-hd",\ 545 .property = "discard_granularity",\ 546 .value = stringify(0),\ 547 },{\ 548 .driver = "ide-cd",\ 549 .property = "discard_granularity",\ 550 .value = stringify(0),\ 551 },{\ 552 .driver = "ide-drive",\ 553 .property = "discard_granularity",\ 554 .value = stringify(0),\ 555 },{\ 556 .driver = "virtio-blk-pci",\ 557 .property = "discard_granularity",\ 558 .value = stringify(0),\ 559 },{\ 560 .driver = "virtio-serial-pci",\ 561 .property = "vectors",\ 562 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\ 563 .value = stringify(0xFFFFFFFF),\ 564 },{ \ 565 .driver = "virtio-net-pci", \ 566 .property = "ctrl_guest_offloads", \ 567 .value = "off", \ 568 },{\ 569 .driver = "e1000",\ 570 .property = "romfile",\ 571 .value = "pxe-e1000.rom",\ 572 },{\ 573 .driver = "ne2k_pci",\ 574 .property = "romfile",\ 575 .value = "pxe-ne2k_pci.rom",\ 576 },{\ 577 .driver = "pcnet",\ 578 .property = "romfile",\ 579 .value = "pxe-pcnet.rom",\ 580 },{\ 581 .driver = "rtl8139",\ 582 .property = "romfile",\ 583 .value = "pxe-rtl8139.rom",\ 584 },{\ 585 .driver = "virtio-net-pci",\ 586 .property = "romfile",\ 587 .value = "pxe-virtio.rom",\ 588 },{\ 589 .driver = "486-" TYPE_X86_CPU,\ 590 .property = "model",\ 591 .value = stringify(0),\ 592 }, 593 594 static inline void pc_common_machine_options(MachineClass *m) 595 { 596 m->default_boot_order = "cad"; 597 } 598 599 static inline void pc_default_machine_options(MachineClass *m) 600 { 601 pc_common_machine_options(m); 602 m->hot_add_cpu = pc_hot_add_cpu; 603 m->max_cpus = 255; 604 } 605 606 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 607 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 608 { \ 609 MachineClass *mc = MACHINE_CLASS(oc); \ 610 optsfn(mc); \ 611 mc->name = namestr; \ 612 mc->init = initfn; \ 613 } \ 614 static const TypeInfo pc_machine_type_##suffix = { \ 615 .name = namestr TYPE_MACHINE_SUFFIX, \ 616 .parent = TYPE_PC_MACHINE, \ 617 .class_init = pc_machine_##suffix##_class_init, \ 618 }; \ 619 static void pc_machine_init_##suffix(void) \ 620 { \ 621 type_register(&pc_machine_type_##suffix); \ 622 } \ 623 machine_init(pc_machine_init_##suffix) 624 625 #define SET_MACHINE_COMPAT(m, COMPAT) do { \ 626 static GlobalProperty props[] = { \ 627 COMPAT \ 628 { /* end of list */ } \ 629 }; \ 630 (m)->compat_props = props; \ 631 } while (0) 632 633 #endif 634