1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu/notify.h" 5 #include "qapi/qapi-types-common.h" 6 #include "qemu/uuid.h" 7 #include "hw/boards.h" 8 #include "hw/block/fdc.h" 9 #include "hw/block/flash.h" 10 #include "hw/i386/x86.h" 11 12 #include "hw/acpi/acpi_dev_interface.h" 13 #include "hw/hotplug.h" 14 #include "qom/object.h" 15 16 #define HPET_INTCAP "hpet-intcap" 17 18 /** 19 * PCMachineState: 20 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 21 * @boot_cpus: number of present VCPUs 22 */ 23 typedef struct PCMachineState { 24 /*< private >*/ 25 X86MachineState parent_obj; 26 27 /* <public> */ 28 29 /* State for other subsystems/APIs: */ 30 Notifier machine_done; 31 32 /* Pointers to devices and objects: */ 33 PCIBus *bus; 34 I2CBus *smbus; 35 PFlashCFI01 *flash[2]; 36 ISADevice *pcspk; 37 38 /* Configuration options: */ 39 uint64_t max_ram_below_4g; 40 OnOffAuto vmport; 41 42 bool acpi_build_enabled; 43 bool smbus_enabled; 44 bool sata_enabled; 45 bool pit_enabled; 46 bool hpet_enabled; 47 uint64_t max_fw_size; 48 49 /* NUMA information: */ 50 uint64_t numa_nodes; 51 uint64_t *node_mem; 52 53 /* ACPI Memory hotplug IO base address */ 54 hwaddr memhp_io_base; 55 } PCMachineState; 56 57 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 58 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 59 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" 60 #define PC_MACHINE_VMPORT "vmport" 61 #define PC_MACHINE_SMBUS "smbus" 62 #define PC_MACHINE_SATA "sata" 63 #define PC_MACHINE_PIT "pit" 64 #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" 65 /** 66 * PCMachineClass: 67 * 68 * Compat fields: 69 * 70 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 71 * backend's alignment value if provided 72 * @acpi_data_size: Size of the chunk of memory at the top of RAM 73 * for the BIOS ACPI tables and other BIOS 74 * datastructures. 75 * @gigabyte_align: Make sure that guest addresses aligned at 76 * 1Gbyte boundaries get mapped to host 77 * addresses aligned at 1Gbyte boundaries. This 78 * way we can use 1GByte pages in the host. 79 * 80 */ 81 struct PCMachineClass { 82 /*< private >*/ 83 X86MachineClass parent_class; 84 85 /*< public >*/ 86 87 /* Device configuration: */ 88 bool pci_enabled; 89 bool kvmclock_enabled; 90 const char *default_nic_model; 91 92 /* Compat options: */ 93 94 /* Default CPU model version. See x86_cpu_set_default_version(). */ 95 int default_cpu_version; 96 97 /* ACPI compat: */ 98 bool has_acpi_build; 99 bool rsdp_in_ram; 100 int legacy_acpi_table_size; 101 unsigned acpi_data_size; 102 bool do_not_add_smb_acpi; 103 int pci_root_uid; 104 105 /* SMBIOS compat: */ 106 bool smbios_defaults; 107 bool smbios_legacy_mode; 108 bool smbios_uuid_encoded; 109 110 /* RAM / address space compat: */ 111 bool gigabyte_align; 112 bool has_reserved_memory; 113 bool enforce_aligned_dimm; 114 bool broken_reserved_end; 115 116 /* generate legacy CPU hotplug AML */ 117 bool legacy_cpu_hotplug; 118 119 /* use DMA capable linuxboot option rom */ 120 bool linuxboot_dma_enabled; 121 122 /* use PVH to load kernels that support this feature */ 123 bool pvh_enabled; 124 125 /* create kvmclock device even when KVM PV features are not exposed */ 126 bool kvmclock_create_always; 127 }; 128 129 #define TYPE_PC_MACHINE "generic-pc-machine" 130 OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE) 131 132 /* ioapic.c */ 133 134 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled); 135 136 /* pc.c */ 137 extern int fd_bootchk; 138 139 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 140 141 void pc_guest_info_init(PCMachineState *pcms); 142 143 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 144 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 145 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 146 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 147 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 148 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 149 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 150 151 152 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 153 MemoryRegion *pci_address_space); 154 155 void xen_load_linux(PCMachineState *pcms); 156 void pc_memory_init(PCMachineState *pcms, 157 MemoryRegion *system_memory, 158 MemoryRegion *rom_memory, 159 MemoryRegion **ram_memory); 160 uint64_t pc_pci_hole64_start(void); 161 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 162 void pc_basic_device_init(struct PCMachineState *pcms, 163 ISABus *isa_bus, qemu_irq *gsi, 164 ISADevice **rtc_state, 165 bool create_fdctrl, 166 uint32_t hpet_irqs); 167 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 168 void pc_cmos_init(PCMachineState *pcms, 169 BusState *ide0, BusState *ide1, 170 ISADevice *s); 171 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 172 void pc_pci_device_init(PCIBus *pci_bus); 173 174 typedef void (*cpu_set_smm_t)(int smm, void *arg); 175 176 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs); 177 178 ISADevice *pc_find_fdc0(void); 179 180 /* port92.c */ 181 #define PORT92_A20_LINE "a20" 182 183 #define TYPE_PORT92 "port92" 184 185 /* pc_sysfw.c */ 186 void pc_system_flash_create(PCMachineState *pcms); 187 void pc_system_flash_cleanup_unused(PCMachineState *pcms); 188 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 189 bool pc_system_ovmf_table_find(const char *entry, uint8_t **data, 190 int *data_len); 191 192 193 /* acpi-build.c */ 194 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 195 const CPUArchIdList *apic_ids, GArray *entry); 196 197 extern GlobalProperty pc_compat_6_0[]; 198 extern const size_t pc_compat_6_0_len; 199 200 extern GlobalProperty pc_compat_5_2[]; 201 extern const size_t pc_compat_5_2_len; 202 203 extern GlobalProperty pc_compat_5_1[]; 204 extern const size_t pc_compat_5_1_len; 205 206 extern GlobalProperty pc_compat_5_0[]; 207 extern const size_t pc_compat_5_0_len; 208 209 extern GlobalProperty pc_compat_4_2[]; 210 extern const size_t pc_compat_4_2_len; 211 212 extern GlobalProperty pc_compat_4_1[]; 213 extern const size_t pc_compat_4_1_len; 214 215 extern GlobalProperty pc_compat_4_0[]; 216 extern const size_t pc_compat_4_0_len; 217 218 extern GlobalProperty pc_compat_3_1[]; 219 extern const size_t pc_compat_3_1_len; 220 221 extern GlobalProperty pc_compat_3_0[]; 222 extern const size_t pc_compat_3_0_len; 223 224 extern GlobalProperty pc_compat_2_12[]; 225 extern const size_t pc_compat_2_12_len; 226 227 extern GlobalProperty pc_compat_2_11[]; 228 extern const size_t pc_compat_2_11_len; 229 230 extern GlobalProperty pc_compat_2_10[]; 231 extern const size_t pc_compat_2_10_len; 232 233 extern GlobalProperty pc_compat_2_9[]; 234 extern const size_t pc_compat_2_9_len; 235 236 extern GlobalProperty pc_compat_2_8[]; 237 extern const size_t pc_compat_2_8_len; 238 239 extern GlobalProperty pc_compat_2_7[]; 240 extern const size_t pc_compat_2_7_len; 241 242 extern GlobalProperty pc_compat_2_6[]; 243 extern const size_t pc_compat_2_6_len; 244 245 extern GlobalProperty pc_compat_2_5[]; 246 extern const size_t pc_compat_2_5_len; 247 248 extern GlobalProperty pc_compat_2_4[]; 249 extern const size_t pc_compat_2_4_len; 250 251 extern GlobalProperty pc_compat_2_3[]; 252 extern const size_t pc_compat_2_3_len; 253 254 extern GlobalProperty pc_compat_2_2[]; 255 extern const size_t pc_compat_2_2_len; 256 257 extern GlobalProperty pc_compat_2_1[]; 258 extern const size_t pc_compat_2_1_len; 259 260 extern GlobalProperty pc_compat_2_0[]; 261 extern const size_t pc_compat_2_0_len; 262 263 extern GlobalProperty pc_compat_1_7[]; 264 extern const size_t pc_compat_1_7_len; 265 266 extern GlobalProperty pc_compat_1_6[]; 267 extern const size_t pc_compat_1_6_len; 268 269 extern GlobalProperty pc_compat_1_5[]; 270 extern const size_t pc_compat_1_5_len; 271 272 extern GlobalProperty pc_compat_1_4[]; 273 extern const size_t pc_compat_1_4_len; 274 275 /* Helper for setting model-id for CPU models that changed model-id 276 * depending on QEMU versions up to QEMU 2.4. 277 */ 278 #define PC_CPU_MODEL_IDS(v) \ 279 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 280 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 281 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 282 283 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 284 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 285 { \ 286 MachineClass *mc = MACHINE_CLASS(oc); \ 287 optsfn(mc); \ 288 mc->init = initfn; \ 289 } \ 290 static const TypeInfo pc_machine_type_##suffix = { \ 291 .name = namestr TYPE_MACHINE_SUFFIX, \ 292 .parent = TYPE_PC_MACHINE, \ 293 .class_init = pc_machine_##suffix##_class_init, \ 294 }; \ 295 static void pc_machine_init_##suffix(void) \ 296 { \ 297 type_register(&pc_machine_type_##suffix); \ 298 } \ 299 type_init(pc_machine_init_##suffix) 300 301 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); 302 #endif 303