1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu/notify.h" 5 #include "qapi/qapi-types-common.h" 6 #include "qemu/uuid.h" 7 #include "hw/boards.h" 8 #include "hw/block/fdc.h" 9 #include "hw/block/flash.h" 10 #include "hw/i386/x86.h" 11 12 #include "hw/acpi/acpi_dev_interface.h" 13 #include "hw/hotplug.h" 14 #include "qom/object.h" 15 #include "hw/i386/sgx-epc.h" 16 #include "hw/firmware/smbios.h" 17 #include "hw/cxl/cxl.h" 18 19 #define HPET_INTCAP "hpet-intcap" 20 21 /** 22 * PCMachineState: 23 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 24 * @boot_cpus: number of present VCPUs 25 */ 26 typedef struct PCMachineState { 27 /*< private >*/ 28 X86MachineState parent_obj; 29 30 /* <public> */ 31 32 /* State for other subsystems/APIs: */ 33 Notifier machine_done; 34 35 /* Pointers to devices and objects: */ 36 PCIBus *bus; 37 I2CBus *smbus; 38 PFlashCFI01 *flash[2]; 39 ISADevice *pcspk; 40 DeviceState *iommu; 41 42 /* Configuration options: */ 43 uint64_t max_ram_below_4g; 44 OnOffAuto vmport; 45 SmbiosEntryPointType smbios_entry_point_type; 46 47 bool acpi_build_enabled; 48 bool smbus_enabled; 49 bool sata_enabled; 50 bool hpet_enabled; 51 bool i8042_enabled; 52 bool default_bus_bypass_iommu; 53 uint64_t max_fw_size; 54 55 /* ACPI Memory hotplug IO base address */ 56 hwaddr memhp_io_base; 57 58 SGXEPCState sgx_epc; 59 CXLState cxl_devices_state; 60 } PCMachineState; 61 62 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 63 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 64 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" 65 #define PC_MACHINE_VMPORT "vmport" 66 #define PC_MACHINE_SMBUS "smbus" 67 #define PC_MACHINE_SATA "sata" 68 #define PC_MACHINE_I8042 "i8042" 69 #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" 70 #define PC_MACHINE_SMBIOS_EP "smbios-entry-point-type" 71 72 /** 73 * PCMachineClass: 74 * 75 * Compat fields: 76 * 77 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 78 * backend's alignment value if provided 79 * @acpi_data_size: Size of the chunk of memory at the top of RAM 80 * for the BIOS ACPI tables and other BIOS 81 * datastructures. 82 * @gigabyte_align: Make sure that guest addresses aligned at 83 * 1Gbyte boundaries get mapped to host 84 * addresses aligned at 1Gbyte boundaries. This 85 * way we can use 1GByte pages in the host. 86 * 87 */ 88 struct PCMachineClass { 89 /*< private >*/ 90 X86MachineClass parent_class; 91 92 /*< public >*/ 93 94 /* Device configuration: */ 95 bool pci_enabled; 96 bool kvmclock_enabled; 97 const char *default_nic_model; 98 99 /* Compat options: */ 100 101 /* Default CPU model version. See x86_cpu_set_default_version(). */ 102 int default_cpu_version; 103 104 /* ACPI compat: */ 105 bool has_acpi_build; 106 bool rsdp_in_ram; 107 int legacy_acpi_table_size; 108 unsigned acpi_data_size; 109 int pci_root_uid; 110 111 /* SMBIOS compat: */ 112 bool smbios_defaults; 113 bool smbios_legacy_mode; 114 bool smbios_uuid_encoded; 115 116 /* RAM / address space compat: */ 117 bool gigabyte_align; 118 bool has_reserved_memory; 119 bool enforce_aligned_dimm; 120 bool broken_reserved_end; 121 bool enforce_amd_1tb_hole; 122 123 /* generate legacy CPU hotplug AML */ 124 bool legacy_cpu_hotplug; 125 126 /* use PVH to load kernels that support this feature */ 127 bool pvh_enabled; 128 129 /* create kvmclock device even when KVM PV features are not exposed */ 130 bool kvmclock_create_always; 131 132 /* skip passing an rng seed for legacy machines */ 133 bool legacy_no_rng_seed; 134 }; 135 136 #define TYPE_PC_MACHINE "generic-pc-machine" 137 OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE) 138 139 /* ioapic.c */ 140 141 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled); 142 143 /* pc.c */ 144 extern int fd_bootchk; 145 146 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 147 148 void pc_guest_info_init(PCMachineState *pcms); 149 150 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 151 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 152 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 153 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 154 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 155 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 156 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 157 158 159 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 160 MemoryRegion *pci_address_space); 161 162 void xen_load_linux(PCMachineState *pcms); 163 void pc_memory_init(PCMachineState *pcms, 164 MemoryRegion *system_memory, 165 MemoryRegion *rom_memory, 166 MemoryRegion **ram_memory, 167 uint64_t pci_hole64_size); 168 uint64_t pc_pci_hole64_start(void); 169 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 170 void pc_basic_device_init(struct PCMachineState *pcms, 171 ISABus *isa_bus, qemu_irq *gsi, 172 ISADevice **rtc_state, 173 bool create_fdctrl, 174 uint32_t hpet_irqs); 175 void pc_cmos_init(PCMachineState *pcms, 176 BusState *ide0, BusState *ide1, 177 ISADevice *s); 178 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 179 180 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs); 181 182 /* port92.c */ 183 #define PORT92_A20_LINE "a20" 184 185 #define TYPE_PORT92 "port92" 186 187 /* pc_sysfw.c */ 188 void pc_system_flash_create(PCMachineState *pcms); 189 void pc_system_flash_cleanup_unused(PCMachineState *pcms); 190 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 191 bool pc_system_ovmf_table_find(const char *entry, uint8_t **data, 192 int *data_len); 193 void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size); 194 195 /* hw/i386/acpi-common.c */ 196 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 197 const CPUArchIdList *apic_ids, GArray *entry, 198 bool force_enabled); 199 200 /* sgx.c */ 201 void pc_machine_init_sgx_epc(PCMachineState *pcms); 202 203 extern GlobalProperty pc_compat_7_1[]; 204 extern const size_t pc_compat_7_1_len; 205 206 extern GlobalProperty pc_compat_7_0[]; 207 extern const size_t pc_compat_7_0_len; 208 209 extern GlobalProperty pc_compat_6_2[]; 210 extern const size_t pc_compat_6_2_len; 211 212 extern GlobalProperty pc_compat_6_1[]; 213 extern const size_t pc_compat_6_1_len; 214 215 extern GlobalProperty pc_compat_6_0[]; 216 extern const size_t pc_compat_6_0_len; 217 218 extern GlobalProperty pc_compat_5_2[]; 219 extern const size_t pc_compat_5_2_len; 220 221 extern GlobalProperty pc_compat_5_1[]; 222 extern const size_t pc_compat_5_1_len; 223 224 extern GlobalProperty pc_compat_5_0[]; 225 extern const size_t pc_compat_5_0_len; 226 227 extern GlobalProperty pc_compat_4_2[]; 228 extern const size_t pc_compat_4_2_len; 229 230 extern GlobalProperty pc_compat_4_1[]; 231 extern const size_t pc_compat_4_1_len; 232 233 extern GlobalProperty pc_compat_4_0[]; 234 extern const size_t pc_compat_4_0_len; 235 236 extern GlobalProperty pc_compat_3_1[]; 237 extern const size_t pc_compat_3_1_len; 238 239 extern GlobalProperty pc_compat_3_0[]; 240 extern const size_t pc_compat_3_0_len; 241 242 extern GlobalProperty pc_compat_2_12[]; 243 extern const size_t pc_compat_2_12_len; 244 245 extern GlobalProperty pc_compat_2_11[]; 246 extern const size_t pc_compat_2_11_len; 247 248 extern GlobalProperty pc_compat_2_10[]; 249 extern const size_t pc_compat_2_10_len; 250 251 extern GlobalProperty pc_compat_2_9[]; 252 extern const size_t pc_compat_2_9_len; 253 254 extern GlobalProperty pc_compat_2_8[]; 255 extern const size_t pc_compat_2_8_len; 256 257 extern GlobalProperty pc_compat_2_7[]; 258 extern const size_t pc_compat_2_7_len; 259 260 extern GlobalProperty pc_compat_2_6[]; 261 extern const size_t pc_compat_2_6_len; 262 263 extern GlobalProperty pc_compat_2_5[]; 264 extern const size_t pc_compat_2_5_len; 265 266 extern GlobalProperty pc_compat_2_4[]; 267 extern const size_t pc_compat_2_4_len; 268 269 extern GlobalProperty pc_compat_2_3[]; 270 extern const size_t pc_compat_2_3_len; 271 272 extern GlobalProperty pc_compat_2_2[]; 273 extern const size_t pc_compat_2_2_len; 274 275 extern GlobalProperty pc_compat_2_1[]; 276 extern const size_t pc_compat_2_1_len; 277 278 extern GlobalProperty pc_compat_2_0[]; 279 extern const size_t pc_compat_2_0_len; 280 281 extern GlobalProperty pc_compat_1_7[]; 282 extern const size_t pc_compat_1_7_len; 283 284 extern GlobalProperty pc_compat_1_6[]; 285 extern const size_t pc_compat_1_6_len; 286 287 extern GlobalProperty pc_compat_1_5[]; 288 extern const size_t pc_compat_1_5_len; 289 290 extern GlobalProperty pc_compat_1_4[]; 291 extern const size_t pc_compat_1_4_len; 292 293 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 294 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 295 { \ 296 MachineClass *mc = MACHINE_CLASS(oc); \ 297 optsfn(mc); \ 298 mc->init = initfn; \ 299 } \ 300 static const TypeInfo pc_machine_type_##suffix = { \ 301 .name = namestr TYPE_MACHINE_SUFFIX, \ 302 .parent = TYPE_PC_MACHINE, \ 303 .class_init = pc_machine_##suffix##_class_init, \ 304 }; \ 305 static void pc_machine_init_##suffix(void) \ 306 { \ 307 type_register(&pc_machine_type_##suffix); \ 308 } \ 309 type_init(pc_machine_init_##suffix) 310 311 #endif 312