1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu-common.h" 5 #include "exec/memory.h" 6 #include "exec/ioport.h" 7 #include "hw/isa/isa.h" 8 #include "hw/block/fdc.h" 9 #include "net/net.h" 10 #include "hw/i386/ioapic.h" 11 12 /* PC-style peripherals (also used by other machines). */ 13 14 /* parallel.c */ 15 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr) 16 { 17 DeviceState *dev; 18 ISADevice *isadev; 19 20 isadev = isa_try_create(bus, "isa-parallel"); 21 if (!isadev) { 22 return false; 23 } 24 dev = DEVICE(isadev); 25 qdev_prop_set_uint32(dev, "index", index); 26 qdev_prop_set_chr(dev, "chardev", chr); 27 if (qdev_init(dev) < 0) { 28 return false; 29 } 30 return true; 31 } 32 33 bool parallel_mm_init(MemoryRegion *address_space, 34 hwaddr base, int it_shift, qemu_irq irq, 35 CharDriverState *chr); 36 37 /* i8259.c */ 38 39 extern DeviceState *isa_pic; 40 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); 41 qemu_irq *kvm_i8259_init(ISABus *bus); 42 int pic_read_irq(DeviceState *d); 43 int pic_get_output(DeviceState *d); 44 void pic_info(Monitor *mon, const QDict *qdict); 45 void irq_info(Monitor *mon, const QDict *qdict); 46 47 /* Global System Interrupts */ 48 49 #define GSI_NUM_PINS IOAPIC_NUM_PINS 50 51 typedef struct GSIState { 52 qemu_irq i8259_irq[ISA_NUM_IRQS]; 53 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 54 } GSIState; 55 56 void gsi_handler(void *opaque, int n, int level); 57 58 /* vmport.c */ 59 static inline void vmport_init(ISABus *bus) 60 { 61 isa_create_simple(bus, "vmport"); 62 } 63 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque); 64 void vmmouse_get_data(uint32_t *data); 65 void vmmouse_set_data(const uint32_t *data); 66 67 /* pckbd.c */ 68 69 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); 70 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 71 MemoryRegion *region, ram_addr_t size, 72 hwaddr mask); 73 void i8042_isa_mouse_fake_event(void *opaque); 74 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out); 75 76 /* pc.c */ 77 extern int fd_bootchk; 78 79 void pc_register_ferr_irq(qemu_irq irq); 80 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 81 82 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge); 83 void pc_hot_add_cpu(const int64_t id, Error **errp); 84 void pc_acpi_init(const char *default_dsdt); 85 FWCfgState *pc_memory_init(MemoryRegion *system_memory, 86 const char *kernel_filename, 87 const char *kernel_cmdline, 88 const char *initrd_filename, 89 ram_addr_t below_4g_mem_size, 90 ram_addr_t above_4g_mem_size, 91 MemoryRegion *rom_memory, 92 MemoryRegion **ram_memory); 93 qemu_irq *pc_allocate_cpu_irq(void); 94 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 95 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 96 ISADevice **rtc_state, 97 ISADevice **floppy, 98 bool no_vmport); 99 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 100 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 101 const char *boot_device, 102 ISADevice *floppy, BusState *ide0, BusState *ide1, 103 ISADevice *s); 104 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus); 105 void pc_pci_device_init(PCIBus *pci_bus); 106 107 typedef void (*cpu_set_smm_t)(int smm, void *arg); 108 void cpu_smm_register(cpu_set_smm_t callback, void *arg); 109 110 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 111 112 /* acpi_piix.c */ 113 114 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 115 qemu_irq sci_irq, qemu_irq smi_irq, 116 int kvm_enabled, FWCfgState *fw_cfg); 117 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); 118 119 /* hpet.c */ 120 extern int no_hpet; 121 122 /* piix_pci.c */ 123 struct PCII440FXState; 124 typedef struct PCII440FXState PCII440FXState; 125 126 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, 127 ISABus **isa_bus, qemu_irq *pic, 128 MemoryRegion *address_space_mem, 129 MemoryRegion *address_space_io, 130 ram_addr_t ram_size, 131 hwaddr pci_hole_start, 132 hwaddr pci_hole_size, 133 hwaddr pci_hole64_start, 134 hwaddr pci_hole64_size, 135 MemoryRegion *pci_memory, 136 MemoryRegion *ram_memory); 137 138 /* piix4.c */ 139 extern PCIDevice *piix4_dev; 140 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); 141 142 /* vga.c */ 143 enum vga_retrace_method { 144 VGA_RETRACE_DUMB, 145 VGA_RETRACE_PRECISE 146 }; 147 148 extern enum vga_retrace_method vga_retrace_method; 149 150 int isa_vga_mm_init(hwaddr vram_base, 151 hwaddr ctrl_base, int it_shift, 152 MemoryRegion *address_space); 153 154 /* ne2000.c */ 155 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) 156 { 157 DeviceState *dev; 158 ISADevice *isadev; 159 160 qemu_check_nic_model(nd, "ne2k_isa"); 161 162 isadev = isa_try_create(bus, "ne2k_isa"); 163 if (!isadev) { 164 return false; 165 } 166 dev = DEVICE(isadev); 167 qdev_prop_set_uint32(dev, "iobase", base); 168 qdev_prop_set_uint32(dev, "irq", irq); 169 qdev_set_nic_properties(dev, nd); 170 qdev_init_nofail(dev); 171 return true; 172 } 173 174 /* pc_sysfw.c */ 175 void pc_system_firmware_init(MemoryRegion *rom_memory); 176 177 /* pvpanic.c */ 178 int pvpanic_init(ISABus *bus); 179 180 /* e820 types */ 181 #define E820_RAM 1 182 #define E820_RESERVED 2 183 #define E820_ACPI 3 184 #define E820_NVS 4 185 #define E820_UNUSABLE 5 186 187 int e820_add_entry(uint64_t, uint64_t, uint32_t); 188 189 #define PC_COMPAT_1_5 \ 190 {\ 191 .driver = "Conroe-" TYPE_X86_CPU,\ 192 .property = "model",\ 193 .value = stringify(2),\ 194 },{\ 195 .driver = "Conroe-" TYPE_X86_CPU,\ 196 .property = "level",\ 197 .value = stringify(2),\ 198 },{\ 199 .driver = "Penryn-" TYPE_X86_CPU,\ 200 .property = "model",\ 201 .value = stringify(2),\ 202 },{\ 203 .driver = "Penryn-" TYPE_X86_CPU,\ 204 .property = "level",\ 205 .value = stringify(2),\ 206 },{\ 207 .driver = "Nehalem-" TYPE_X86_CPU,\ 208 .property = "model",\ 209 .value = stringify(2),\ 210 },{\ 211 .driver = "Nehalem-" TYPE_X86_CPU,\ 212 .property = "level",\ 213 .value = stringify(2),\ 214 } 215 216 #define PC_COMPAT_1_4 \ 217 PC_COMPAT_1_5, \ 218 {\ 219 .driver = "scsi-hd",\ 220 .property = "discard_granularity",\ 221 .value = stringify(0),\ 222 },{\ 223 .driver = "scsi-cd",\ 224 .property = "discard_granularity",\ 225 .value = stringify(0),\ 226 },{\ 227 .driver = "scsi-disk",\ 228 .property = "discard_granularity",\ 229 .value = stringify(0),\ 230 },{\ 231 .driver = "ide-hd",\ 232 .property = "discard_granularity",\ 233 .value = stringify(0),\ 234 },{\ 235 .driver = "ide-cd",\ 236 .property = "discard_granularity",\ 237 .value = stringify(0),\ 238 },{\ 239 .driver = "ide-drive",\ 240 .property = "discard_granularity",\ 241 .value = stringify(0),\ 242 },{\ 243 .driver = "virtio-blk-pci",\ 244 .property = "discard_granularity",\ 245 .value = stringify(0),\ 246 },{\ 247 .driver = "virtio-serial-pci",\ 248 .property = "vectors",\ 249 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\ 250 .value = stringify(0xFFFFFFFF),\ 251 },{ \ 252 .driver = "virtio-net-pci", \ 253 .property = "ctrl_guest_offloads", \ 254 .value = "off", \ 255 },{\ 256 .driver = "e1000",\ 257 .property = "romfile",\ 258 .value = "pxe-e1000.rom",\ 259 },{\ 260 .driver = "ne2k_pci",\ 261 .property = "romfile",\ 262 .value = "pxe-ne2k_pci.rom",\ 263 },{\ 264 .driver = "pcnet",\ 265 .property = "romfile",\ 266 .value = "pxe-pcnet.rom",\ 267 },{\ 268 .driver = "rtl8139",\ 269 .property = "romfile",\ 270 .value = "pxe-rtl8139.rom",\ 271 },{\ 272 .driver = "virtio-net-pci",\ 273 .property = "romfile",\ 274 .value = "pxe-virtio.rom",\ 275 },{\ 276 .driver = "486-" TYPE_X86_CPU,\ 277 .property = "model",\ 278 .value = stringify(0),\ 279 } 280 281 #endif 282