1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu-common.h" 5 #include "exec/memory.h" 6 #include "hw/isa/isa.h" 7 #include "hw/block/fdc.h" 8 #include "net/net.h" 9 #include "hw/i386/ioapic.h" 10 11 #include "qemu/range.h" 12 #include "qemu/bitmap.h" 13 #include "sysemu/sysemu.h" 14 #include "hw/pci/pci.h" 15 16 /* PC-style peripherals (also used by other machines). */ 17 18 typedef struct PcPciInfo { 19 Range w32; 20 Range w64; 21 } PcPciInfo; 22 23 #define ACPI_PM_PROP_S3_DISABLED "disable_s3" 24 #define ACPI_PM_PROP_S4_DISABLED "disable_s4" 25 #define ACPI_PM_PROP_S4_VAL "s4_val" 26 #define ACPI_PM_PROP_SCI_INT "sci_int" 27 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd" 28 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd" 29 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base" 30 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk" 31 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" 32 33 struct PcGuestInfo { 34 bool has_pci_info; 35 bool isapc_ram_fw; 36 hwaddr ram_size; 37 unsigned apic_id_limit; 38 bool apic_xrupt_override; 39 uint64_t numa_nodes; 40 uint64_t *node_mem; 41 uint64_t *node_cpu; 42 FWCfgState *fw_cfg; 43 bool has_acpi_build; 44 }; 45 46 /* parallel.c */ 47 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr) 48 { 49 DeviceState *dev; 50 ISADevice *isadev; 51 52 isadev = isa_try_create(bus, "isa-parallel"); 53 if (!isadev) { 54 return false; 55 } 56 dev = DEVICE(isadev); 57 qdev_prop_set_uint32(dev, "index", index); 58 qdev_prop_set_chr(dev, "chardev", chr); 59 if (qdev_init(dev) < 0) { 60 return false; 61 } 62 return true; 63 } 64 65 bool parallel_mm_init(MemoryRegion *address_space, 66 hwaddr base, int it_shift, qemu_irq irq, 67 CharDriverState *chr); 68 69 /* i8259.c */ 70 71 extern DeviceState *isa_pic; 72 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); 73 qemu_irq *kvm_i8259_init(ISABus *bus); 74 int pic_read_irq(DeviceState *d); 75 int pic_get_output(DeviceState *d); 76 void pic_info(Monitor *mon, const QDict *qdict); 77 void irq_info(Monitor *mon, const QDict *qdict); 78 79 /* Global System Interrupts */ 80 81 #define GSI_NUM_PINS IOAPIC_NUM_PINS 82 83 typedef struct GSIState { 84 qemu_irq i8259_irq[ISA_NUM_IRQS]; 85 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 86 } GSIState; 87 88 void gsi_handler(void *opaque, int n, int level); 89 90 /* vmport.c */ 91 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); 92 93 static inline void vmport_init(ISABus *bus) 94 { 95 isa_create_simple(bus, "vmport"); 96 } 97 98 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); 99 void vmmouse_get_data(uint32_t *data); 100 void vmmouse_set_data(const uint32_t *data); 101 102 /* pckbd.c */ 103 104 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); 105 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 106 MemoryRegion *region, ram_addr_t size, 107 hwaddr mask); 108 void i8042_isa_mouse_fake_event(void *opaque); 109 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out); 110 111 /* pc.c */ 112 extern int fd_bootchk; 113 114 void pc_register_ferr_irq(qemu_irq irq); 115 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 116 117 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge); 118 void pc_hot_add_cpu(const int64_t id, Error **errp); 119 void pc_acpi_init(const char *default_dsdt); 120 121 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 122 ram_addr_t above_4g_mem_size); 123 124 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 125 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 126 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 127 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 128 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 129 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL) 130 131 132 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 133 MemoryRegion *pci_address_space); 134 135 FWCfgState *pc_memory_init(MemoryRegion *system_memory, 136 const char *kernel_filename, 137 const char *kernel_cmdline, 138 const char *initrd_filename, 139 ram_addr_t below_4g_mem_size, 140 ram_addr_t above_4g_mem_size, 141 MemoryRegion *rom_memory, 142 MemoryRegion **ram_memory, 143 PcGuestInfo *guest_info); 144 qemu_irq *pc_allocate_cpu_irq(void); 145 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 146 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 147 ISADevice **rtc_state, 148 ISADevice **floppy, 149 bool no_vmport); 150 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 151 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 152 const char *boot_device, 153 ISADevice *floppy, BusState *ide0, BusState *ide1, 154 ISADevice *s); 155 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus); 156 void pc_pci_device_init(PCIBus *pci_bus); 157 158 typedef void (*cpu_set_smm_t)(int smm, void *arg); 159 void cpu_smm_register(cpu_set_smm_t callback, void *arg); 160 161 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 162 163 /* acpi_piix.c */ 164 165 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 166 qemu_irq sci_irq, qemu_irq smi_irq, 167 int kvm_enabled, FWCfgState *fw_cfg); 168 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); 169 170 /* hpet.c */ 171 extern int no_hpet; 172 173 /* piix_pci.c */ 174 struct PCII440FXState; 175 typedef struct PCII440FXState PCII440FXState; 176 177 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, 178 ISABus **isa_bus, qemu_irq *pic, 179 MemoryRegion *address_space_mem, 180 MemoryRegion *address_space_io, 181 ram_addr_t ram_size, 182 ram_addr_t above_4g_mem_size, 183 MemoryRegion *pci_memory, 184 MemoryRegion *ram_memory); 185 186 PCIBus *find_i440fx(void); 187 /* piix4.c */ 188 extern PCIDevice *piix4_dev; 189 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); 190 191 /* vga.c */ 192 enum vga_retrace_method { 193 VGA_RETRACE_DUMB, 194 VGA_RETRACE_PRECISE 195 }; 196 197 extern enum vga_retrace_method vga_retrace_method; 198 199 int isa_vga_mm_init(hwaddr vram_base, 200 hwaddr ctrl_base, int it_shift, 201 MemoryRegion *address_space); 202 203 /* ne2000.c */ 204 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) 205 { 206 DeviceState *dev; 207 ISADevice *isadev; 208 209 qemu_check_nic_model(nd, "ne2k_isa"); 210 211 isadev = isa_try_create(bus, "ne2k_isa"); 212 if (!isadev) { 213 return false; 214 } 215 dev = DEVICE(isadev); 216 qdev_prop_set_uint32(dev, "iobase", base); 217 qdev_prop_set_uint32(dev, "irq", irq); 218 qdev_set_nic_properties(dev, nd); 219 qdev_init_nofail(dev); 220 return true; 221 } 222 223 /* pc_sysfw.c */ 224 void pc_system_firmware_init(MemoryRegion *rom_memory, 225 bool isapc_ram_fw); 226 227 /* pvpanic.c */ 228 uint16_t pvpanic_port(void); 229 230 /* e820 types */ 231 #define E820_RAM 1 232 #define E820_RESERVED 2 233 #define E820_ACPI 3 234 #define E820_NVS 4 235 #define E820_UNUSABLE 5 236 237 int e820_add_entry(uint64_t, uint64_t, uint32_t); 238 239 #define PC_COMPAT_1_6 \ 240 {\ 241 .driver = "e1000",\ 242 .property = "mitigation",\ 243 .value = "off",\ 244 },{\ 245 .driver = "qemu64-" TYPE_X86_CPU,\ 246 .property = "model",\ 247 .value = stringify(2),\ 248 },{\ 249 .driver = "qemu32-" TYPE_X86_CPU,\ 250 .property = "model",\ 251 .value = stringify(3),\ 252 },{\ 253 .driver = "i440FX-pcihost",\ 254 .property = "short_root_bus",\ 255 .value = stringify(1),\ 256 },{\ 257 .driver = "q35-pcihost",\ 258 .property = "short_root_bus",\ 259 .value = stringify(1),\ 260 } 261 262 #define PC_COMPAT_1_5 \ 263 PC_COMPAT_1_6, \ 264 {\ 265 .driver = "Conroe-" TYPE_X86_CPU,\ 266 .property = "model",\ 267 .value = stringify(2),\ 268 },{\ 269 .driver = "Conroe-" TYPE_X86_CPU,\ 270 .property = "level",\ 271 .value = stringify(2),\ 272 },{\ 273 .driver = "Penryn-" TYPE_X86_CPU,\ 274 .property = "model",\ 275 .value = stringify(2),\ 276 },{\ 277 .driver = "Penryn-" TYPE_X86_CPU,\ 278 .property = "level",\ 279 .value = stringify(2),\ 280 },{\ 281 .driver = "Nehalem-" TYPE_X86_CPU,\ 282 .property = "model",\ 283 .value = stringify(2),\ 284 },{\ 285 .driver = "Nehalem-" TYPE_X86_CPU,\ 286 .property = "level",\ 287 .value = stringify(2),\ 288 },{\ 289 .driver = "virtio-net-pci",\ 290 .property = "any_layout",\ 291 .value = "off",\ 292 },{\ 293 .driver = TYPE_X86_CPU,\ 294 .property = "pmu",\ 295 .value = "on",\ 296 },{\ 297 .driver = "i440FX-pcihost",\ 298 .property = "short_root_bus",\ 299 .value = stringify(0),\ 300 },{\ 301 .driver = "q35-pcihost",\ 302 .property = "short_root_bus",\ 303 .value = stringify(0),\ 304 } 305 306 #define PC_COMPAT_1_4 \ 307 PC_COMPAT_1_5, \ 308 {\ 309 .driver = "scsi-hd",\ 310 .property = "discard_granularity",\ 311 .value = stringify(0),\ 312 },{\ 313 .driver = "scsi-cd",\ 314 .property = "discard_granularity",\ 315 .value = stringify(0),\ 316 },{\ 317 .driver = "scsi-disk",\ 318 .property = "discard_granularity",\ 319 .value = stringify(0),\ 320 },{\ 321 .driver = "ide-hd",\ 322 .property = "discard_granularity",\ 323 .value = stringify(0),\ 324 },{\ 325 .driver = "ide-cd",\ 326 .property = "discard_granularity",\ 327 .value = stringify(0),\ 328 },{\ 329 .driver = "ide-drive",\ 330 .property = "discard_granularity",\ 331 .value = stringify(0),\ 332 },{\ 333 .driver = "virtio-blk-pci",\ 334 .property = "discard_granularity",\ 335 .value = stringify(0),\ 336 },{\ 337 .driver = "virtio-serial-pci",\ 338 .property = "vectors",\ 339 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\ 340 .value = stringify(0xFFFFFFFF),\ 341 },{ \ 342 .driver = "virtio-net-pci", \ 343 .property = "ctrl_guest_offloads", \ 344 .value = "off", \ 345 },{\ 346 .driver = "e1000",\ 347 .property = "romfile",\ 348 .value = "pxe-e1000.rom",\ 349 },{\ 350 .driver = "ne2k_pci",\ 351 .property = "romfile",\ 352 .value = "pxe-ne2k_pci.rom",\ 353 },{\ 354 .driver = "pcnet",\ 355 .property = "romfile",\ 356 .value = "pxe-pcnet.rom",\ 357 },{\ 358 .driver = "rtl8139",\ 359 .property = "romfile",\ 360 .value = "pxe-rtl8139.rom",\ 361 },{\ 362 .driver = "virtio-net-pci",\ 363 .property = "romfile",\ 364 .value = "pxe-virtio.rom",\ 365 },{\ 366 .driver = "486-" TYPE_X86_CPU,\ 367 .property = "model",\ 368 .value = stringify(0),\ 369 } 370 371 #define PC_COMMON_MACHINE_OPTIONS \ 372 .default_boot_order = "cad" 373 374 #define PC_DEFAULT_MACHINE_OPTIONS \ 375 PC_COMMON_MACHINE_OPTIONS, \ 376 .hot_add_cpu = pc_hot_add_cpu, \ 377 .max_cpus = 255 378 379 #endif 380