1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu-common.h" 5 #include "exec/memory.h" 6 #include "hw/isa/isa.h" 7 #include "hw/block/fdc.h" 8 #include "net/net.h" 9 #include "hw/i386/ioapic.h" 10 11 #include "qemu/range.h" 12 #include "qemu/bitmap.h" 13 #include "sysemu/sysemu.h" 14 #include "hw/pci/pci.h" 15 16 /* PC-style peripherals (also used by other machines). */ 17 18 typedef struct PcPciInfo { 19 Range w32; 20 Range w64; 21 } PcPciInfo; 22 23 #define ACPI_PM_PROP_S3_DISABLED "disable_s3" 24 #define ACPI_PM_PROP_S4_DISABLED "disable_s4" 25 #define ACPI_PM_PROP_S4_VAL "s4_val" 26 #define ACPI_PM_PROP_SCI_INT "sci_int" 27 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd" 28 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd" 29 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base" 30 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk" 31 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" 32 33 struct PcGuestInfo { 34 bool has_pci_info; 35 bool isapc_ram_fw; 36 hwaddr ram_size; 37 unsigned apic_id_limit; 38 bool apic_xrupt_override; 39 uint64_t numa_nodes; 40 uint64_t *node_mem; 41 uint64_t *node_cpu; 42 FWCfgState *fw_cfg; 43 }; 44 45 /* parallel.c */ 46 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr) 47 { 48 DeviceState *dev; 49 ISADevice *isadev; 50 51 isadev = isa_try_create(bus, "isa-parallel"); 52 if (!isadev) { 53 return false; 54 } 55 dev = DEVICE(isadev); 56 qdev_prop_set_uint32(dev, "index", index); 57 qdev_prop_set_chr(dev, "chardev", chr); 58 if (qdev_init(dev) < 0) { 59 return false; 60 } 61 return true; 62 } 63 64 bool parallel_mm_init(MemoryRegion *address_space, 65 hwaddr base, int it_shift, qemu_irq irq, 66 CharDriverState *chr); 67 68 /* i8259.c */ 69 70 extern DeviceState *isa_pic; 71 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); 72 qemu_irq *kvm_i8259_init(ISABus *bus); 73 int pic_read_irq(DeviceState *d); 74 int pic_get_output(DeviceState *d); 75 void pic_info(Monitor *mon, const QDict *qdict); 76 void irq_info(Monitor *mon, const QDict *qdict); 77 78 /* Global System Interrupts */ 79 80 #define GSI_NUM_PINS IOAPIC_NUM_PINS 81 82 typedef struct GSIState { 83 qemu_irq i8259_irq[ISA_NUM_IRQS]; 84 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 85 } GSIState; 86 87 void gsi_handler(void *opaque, int n, int level); 88 89 /* vmport.c */ 90 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); 91 92 static inline void vmport_init(ISABus *bus) 93 { 94 isa_create_simple(bus, "vmport"); 95 } 96 97 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); 98 void vmmouse_get_data(uint32_t *data); 99 void vmmouse_set_data(const uint32_t *data); 100 101 /* pckbd.c */ 102 103 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); 104 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 105 MemoryRegion *region, ram_addr_t size, 106 hwaddr mask); 107 void i8042_isa_mouse_fake_event(void *opaque); 108 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out); 109 110 /* pc.c */ 111 extern int fd_bootchk; 112 113 void pc_register_ferr_irq(qemu_irq irq); 114 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 115 116 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge); 117 void pc_hot_add_cpu(const int64_t id, Error **errp); 118 void pc_acpi_init(const char *default_dsdt); 119 120 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 121 ram_addr_t above_4g_mem_size); 122 123 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 124 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 125 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 126 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 127 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 128 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL) 129 130 static inline uint64_t pci_host_get_hole64_size(uint64_t pci_hole64_size) 131 { 132 if (pci_hole64_size == DEFAULT_PCI_HOLE64_SIZE) { 133 return 1ULL << 62; 134 } else { 135 return pci_hole64_size; 136 } 137 } 138 139 void pc_init_pci64_hole(PcPciInfo *pci_info, uint64_t pci_hole64_start, 140 uint64_t pci_hole64_size); 141 142 FWCfgState *pc_memory_init(MemoryRegion *system_memory, 143 const char *kernel_filename, 144 const char *kernel_cmdline, 145 const char *initrd_filename, 146 ram_addr_t below_4g_mem_size, 147 ram_addr_t above_4g_mem_size, 148 MemoryRegion *rom_memory, 149 MemoryRegion **ram_memory, 150 PcGuestInfo *guest_info); 151 qemu_irq *pc_allocate_cpu_irq(void); 152 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 153 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 154 ISADevice **rtc_state, 155 ISADevice **floppy, 156 bool no_vmport); 157 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 158 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 159 const char *boot_device, 160 ISADevice *floppy, BusState *ide0, BusState *ide1, 161 ISADevice *s); 162 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus); 163 void pc_pci_device_init(PCIBus *pci_bus); 164 165 typedef void (*cpu_set_smm_t)(int smm, void *arg); 166 void cpu_smm_register(cpu_set_smm_t callback, void *arg); 167 168 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 169 170 /* acpi_piix.c */ 171 172 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 173 qemu_irq sci_irq, qemu_irq smi_irq, 174 int kvm_enabled, FWCfgState *fw_cfg); 175 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); 176 177 /* hpet.c */ 178 extern int no_hpet; 179 180 /* piix_pci.c */ 181 struct PCII440FXState; 182 typedef struct PCII440FXState PCII440FXState; 183 184 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, 185 ISABus **isa_bus, qemu_irq *pic, 186 MemoryRegion *address_space_mem, 187 MemoryRegion *address_space_io, 188 ram_addr_t ram_size, 189 hwaddr pci_hole_start, 190 hwaddr pci_hole_size, 191 ram_addr_t above_4g_mem_size, 192 MemoryRegion *pci_memory, 193 MemoryRegion *ram_memory); 194 195 PCIBus *find_i440fx(void); 196 /* piix4.c */ 197 extern PCIDevice *piix4_dev; 198 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); 199 200 /* vga.c */ 201 enum vga_retrace_method { 202 VGA_RETRACE_DUMB, 203 VGA_RETRACE_PRECISE 204 }; 205 206 extern enum vga_retrace_method vga_retrace_method; 207 208 int isa_vga_mm_init(hwaddr vram_base, 209 hwaddr ctrl_base, int it_shift, 210 MemoryRegion *address_space); 211 212 /* ne2000.c */ 213 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) 214 { 215 DeviceState *dev; 216 ISADevice *isadev; 217 218 qemu_check_nic_model(nd, "ne2k_isa"); 219 220 isadev = isa_try_create(bus, "ne2k_isa"); 221 if (!isadev) { 222 return false; 223 } 224 dev = DEVICE(isadev); 225 qdev_prop_set_uint32(dev, "iobase", base); 226 qdev_prop_set_uint32(dev, "irq", irq); 227 qdev_set_nic_properties(dev, nd); 228 qdev_init_nofail(dev); 229 return true; 230 } 231 232 /* pc_sysfw.c */ 233 void pc_system_firmware_init(MemoryRegion *rom_memory, 234 bool isapc_ram_fw); 235 236 /* pvpanic.c */ 237 void pvpanic_init(ISABus *bus); 238 239 /* e820 types */ 240 #define E820_RAM 1 241 #define E820_RESERVED 2 242 #define E820_ACPI 3 243 #define E820_NVS 4 244 #define E820_UNUSABLE 5 245 246 int e820_add_entry(uint64_t, uint64_t, uint32_t); 247 248 #define PC_COMPAT_1_6 \ 249 {\ 250 .driver = "e1000",\ 251 .property = "mitigation",\ 252 .value = "off",\ 253 } 254 255 #define PC_COMPAT_1_5 \ 256 PC_COMPAT_1_6, \ 257 {\ 258 .driver = "Conroe-" TYPE_X86_CPU,\ 259 .property = "model",\ 260 .value = stringify(2),\ 261 },{\ 262 .driver = "Conroe-" TYPE_X86_CPU,\ 263 .property = "level",\ 264 .value = stringify(2),\ 265 },{\ 266 .driver = "Penryn-" TYPE_X86_CPU,\ 267 .property = "model",\ 268 .value = stringify(2),\ 269 },{\ 270 .driver = "Penryn-" TYPE_X86_CPU,\ 271 .property = "level",\ 272 .value = stringify(2),\ 273 },{\ 274 .driver = "Nehalem-" TYPE_X86_CPU,\ 275 .property = "model",\ 276 .value = stringify(2),\ 277 },{\ 278 .driver = "Nehalem-" TYPE_X86_CPU,\ 279 .property = "level",\ 280 .value = stringify(2),\ 281 },{\ 282 .driver = "virtio-net-pci",\ 283 .property = "any_layout",\ 284 .value = "off",\ 285 },{\ 286 .driver = TYPE_X86_CPU,\ 287 .property = "pmu",\ 288 .value = "on",\ 289 } 290 291 #define PC_COMPAT_1_4 \ 292 PC_COMPAT_1_5, \ 293 {\ 294 .driver = "scsi-hd",\ 295 .property = "discard_granularity",\ 296 .value = stringify(0),\ 297 },{\ 298 .driver = "scsi-cd",\ 299 .property = "discard_granularity",\ 300 .value = stringify(0),\ 301 },{\ 302 .driver = "scsi-disk",\ 303 .property = "discard_granularity",\ 304 .value = stringify(0),\ 305 },{\ 306 .driver = "ide-hd",\ 307 .property = "discard_granularity",\ 308 .value = stringify(0),\ 309 },{\ 310 .driver = "ide-cd",\ 311 .property = "discard_granularity",\ 312 .value = stringify(0),\ 313 },{\ 314 .driver = "ide-drive",\ 315 .property = "discard_granularity",\ 316 .value = stringify(0),\ 317 },{\ 318 .driver = "virtio-blk-pci",\ 319 .property = "discard_granularity",\ 320 .value = stringify(0),\ 321 },{\ 322 .driver = "virtio-serial-pci",\ 323 .property = "vectors",\ 324 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\ 325 .value = stringify(0xFFFFFFFF),\ 326 },{ \ 327 .driver = "virtio-net-pci", \ 328 .property = "ctrl_guest_offloads", \ 329 .value = "off", \ 330 },{\ 331 .driver = "e1000",\ 332 .property = "romfile",\ 333 .value = "pxe-e1000.rom",\ 334 },{\ 335 .driver = "ne2k_pci",\ 336 .property = "romfile",\ 337 .value = "pxe-ne2k_pci.rom",\ 338 },{\ 339 .driver = "pcnet",\ 340 .property = "romfile",\ 341 .value = "pxe-pcnet.rom",\ 342 },{\ 343 .driver = "rtl8139",\ 344 .property = "romfile",\ 345 .value = "pxe-rtl8139.rom",\ 346 },{\ 347 .driver = "virtio-net-pci",\ 348 .property = "romfile",\ 349 .value = "pxe-virtio.rom",\ 350 },{\ 351 .driver = "486-" TYPE_X86_CPU,\ 352 .property = "model",\ 353 .value = stringify(0),\ 354 } 355 356 #define PC_COMMON_MACHINE_OPTIONS \ 357 .default_boot_order = "cad" 358 359 #define PC_DEFAULT_MACHINE_OPTIONS \ 360 PC_COMMON_MACHINE_OPTIONS, \ 361 .hot_add_cpu = pc_hot_add_cpu, \ 362 .max_cpus = 255 363 364 #endif 365