1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu/notify.h" 5 #include "qapi/qapi-types-common.h" 6 #include "qemu/uuid.h" 7 #include "hw/boards.h" 8 #include "hw/block/fdc.h" 9 #include "hw/block/flash.h" 10 #include "hw/i386/x86.h" 11 12 #include "hw/acpi/acpi_dev_interface.h" 13 #include "hw/hotplug.h" 14 #include "qom/object.h" 15 16 #define HPET_INTCAP "hpet-intcap" 17 18 /** 19 * PCMachineState: 20 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 21 * @boot_cpus: number of present VCPUs 22 * @smp_dies: number of dies per one package 23 */ 24 typedef struct PCMachineState { 25 /*< private >*/ 26 X86MachineState parent_obj; 27 28 /* <public> */ 29 30 /* State for other subsystems/APIs: */ 31 Notifier machine_done; 32 33 /* Pointers to devices and objects: */ 34 PCIBus *bus; 35 I2CBus *smbus; 36 PFlashCFI01 *flash[2]; 37 ISADevice *pcspk; 38 39 /* Configuration options: */ 40 uint64_t max_ram_below_4g; 41 OnOffAuto vmport; 42 43 bool acpi_build_enabled; 44 bool smbus_enabled; 45 bool sata_enabled; 46 bool pit_enabled; 47 bool hpet_enabled; 48 uint64_t max_fw_size; 49 char *oem_id; 50 char *oem_table_id; 51 52 /* NUMA information: */ 53 uint64_t numa_nodes; 54 uint64_t *node_mem; 55 56 /* ACPI Memory hotplug IO base address */ 57 hwaddr memhp_io_base; 58 } PCMachineState; 59 60 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 61 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 62 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" 63 #define PC_MACHINE_VMPORT "vmport" 64 #define PC_MACHINE_SMBUS "smbus" 65 #define PC_MACHINE_SATA "sata" 66 #define PC_MACHINE_PIT "pit" 67 #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" 68 #define PC_MACHINE_OEM_ID "oem-id" 69 #define PC_MACHINE_OEM_TABLE_ID "oem-table-id" 70 /** 71 * PCMachineClass: 72 * 73 * Compat fields: 74 * 75 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 76 * backend's alignment value if provided 77 * @acpi_data_size: Size of the chunk of memory at the top of RAM 78 * for the BIOS ACPI tables and other BIOS 79 * datastructures. 80 * @gigabyte_align: Make sure that guest addresses aligned at 81 * 1Gbyte boundaries get mapped to host 82 * addresses aligned at 1Gbyte boundaries. This 83 * way we can use 1GByte pages in the host. 84 * 85 */ 86 struct PCMachineClass { 87 /*< private >*/ 88 X86MachineClass parent_class; 89 90 /*< public >*/ 91 92 /* Device configuration: */ 93 bool pci_enabled; 94 bool kvmclock_enabled; 95 const char *default_nic_model; 96 97 /* Compat options: */ 98 99 /* Default CPU model version. See x86_cpu_set_default_version(). */ 100 int default_cpu_version; 101 102 /* ACPI compat: */ 103 bool has_acpi_build; 104 bool rsdp_in_ram; 105 int legacy_acpi_table_size; 106 unsigned acpi_data_size; 107 bool do_not_add_smb_acpi; 108 int pci_root_uid; 109 110 /* SMBIOS compat: */ 111 bool smbios_defaults; 112 bool smbios_legacy_mode; 113 bool smbios_uuid_encoded; 114 115 /* RAM / address space compat: */ 116 bool gigabyte_align; 117 bool has_reserved_memory; 118 bool enforce_aligned_dimm; 119 bool broken_reserved_end; 120 121 /* generate legacy CPU hotplug AML */ 122 bool legacy_cpu_hotplug; 123 124 /* use DMA capable linuxboot option rom */ 125 bool linuxboot_dma_enabled; 126 127 /* use PVH to load kernels that support this feature */ 128 bool pvh_enabled; 129 130 /* create kvmclock device even when KVM PV features are not exposed */ 131 bool kvmclock_create_always; 132 }; 133 134 #define TYPE_PC_MACHINE "generic-pc-machine" 135 OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE) 136 137 /* ioapic.c */ 138 139 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled); 140 141 /* pc.c */ 142 extern int fd_bootchk; 143 144 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 145 146 void pc_smp_parse(MachineState *ms, QemuOpts *opts); 147 148 void pc_guest_info_init(PCMachineState *pcms); 149 150 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 151 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 152 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 153 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 154 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 155 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 156 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 157 158 159 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 160 MemoryRegion *pci_address_space); 161 162 void xen_load_linux(PCMachineState *pcms); 163 void pc_memory_init(PCMachineState *pcms, 164 MemoryRegion *system_memory, 165 MemoryRegion *rom_memory, 166 MemoryRegion **ram_memory); 167 uint64_t pc_pci_hole64_start(void); 168 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 169 void pc_basic_device_init(struct PCMachineState *pcms, 170 ISABus *isa_bus, qemu_irq *gsi, 171 ISADevice **rtc_state, 172 bool create_fdctrl, 173 uint32_t hpet_irqs); 174 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 175 void pc_cmos_init(PCMachineState *pcms, 176 BusState *ide0, BusState *ide1, 177 ISADevice *s); 178 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 179 void pc_pci_device_init(PCIBus *pci_bus); 180 181 typedef void (*cpu_set_smm_t)(int smm, void *arg); 182 183 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs); 184 185 ISADevice *pc_find_fdc0(void); 186 187 /* port92.c */ 188 #define PORT92_A20_LINE "a20" 189 190 #define TYPE_PORT92 "port92" 191 192 /* pc_sysfw.c */ 193 void pc_system_flash_create(PCMachineState *pcms); 194 void pc_system_flash_cleanup_unused(PCMachineState *pcms); 195 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 196 bool pc_system_ovmf_table_find(const char *entry, uint8_t **data, 197 int *data_len); 198 199 200 /* acpi-build.c */ 201 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 202 const CPUArchIdList *apic_ids, GArray *entry); 203 204 extern GlobalProperty pc_compat_5_2[]; 205 extern const size_t pc_compat_5_2_len; 206 207 extern GlobalProperty pc_compat_5_1[]; 208 extern const size_t pc_compat_5_1_len; 209 210 extern GlobalProperty pc_compat_5_0[]; 211 extern const size_t pc_compat_5_0_len; 212 213 extern GlobalProperty pc_compat_4_2[]; 214 extern const size_t pc_compat_4_2_len; 215 216 extern GlobalProperty pc_compat_4_1[]; 217 extern const size_t pc_compat_4_1_len; 218 219 extern GlobalProperty pc_compat_4_0[]; 220 extern const size_t pc_compat_4_0_len; 221 222 extern GlobalProperty pc_compat_3_1[]; 223 extern const size_t pc_compat_3_1_len; 224 225 extern GlobalProperty pc_compat_3_0[]; 226 extern const size_t pc_compat_3_0_len; 227 228 extern GlobalProperty pc_compat_2_12[]; 229 extern const size_t pc_compat_2_12_len; 230 231 extern GlobalProperty pc_compat_2_11[]; 232 extern const size_t pc_compat_2_11_len; 233 234 extern GlobalProperty pc_compat_2_10[]; 235 extern const size_t pc_compat_2_10_len; 236 237 extern GlobalProperty pc_compat_2_9[]; 238 extern const size_t pc_compat_2_9_len; 239 240 extern GlobalProperty pc_compat_2_8[]; 241 extern const size_t pc_compat_2_8_len; 242 243 extern GlobalProperty pc_compat_2_7[]; 244 extern const size_t pc_compat_2_7_len; 245 246 extern GlobalProperty pc_compat_2_6[]; 247 extern const size_t pc_compat_2_6_len; 248 249 extern GlobalProperty pc_compat_2_5[]; 250 extern const size_t pc_compat_2_5_len; 251 252 extern GlobalProperty pc_compat_2_4[]; 253 extern const size_t pc_compat_2_4_len; 254 255 extern GlobalProperty pc_compat_2_3[]; 256 extern const size_t pc_compat_2_3_len; 257 258 extern GlobalProperty pc_compat_2_2[]; 259 extern const size_t pc_compat_2_2_len; 260 261 extern GlobalProperty pc_compat_2_1[]; 262 extern const size_t pc_compat_2_1_len; 263 264 extern GlobalProperty pc_compat_2_0[]; 265 extern const size_t pc_compat_2_0_len; 266 267 extern GlobalProperty pc_compat_1_7[]; 268 extern const size_t pc_compat_1_7_len; 269 270 extern GlobalProperty pc_compat_1_6[]; 271 extern const size_t pc_compat_1_6_len; 272 273 extern GlobalProperty pc_compat_1_5[]; 274 extern const size_t pc_compat_1_5_len; 275 276 extern GlobalProperty pc_compat_1_4[]; 277 extern const size_t pc_compat_1_4_len; 278 279 /* Helper for setting model-id for CPU models that changed model-id 280 * depending on QEMU versions up to QEMU 2.4. 281 */ 282 #define PC_CPU_MODEL_IDS(v) \ 283 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 284 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 285 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 286 287 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 288 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 289 { \ 290 MachineClass *mc = MACHINE_CLASS(oc); \ 291 optsfn(mc); \ 292 mc->init = initfn; \ 293 } \ 294 static const TypeInfo pc_machine_type_##suffix = { \ 295 .name = namestr TYPE_MACHINE_SUFFIX, \ 296 .parent = TYPE_PC_MACHINE, \ 297 .class_init = pc_machine_##suffix##_class_init, \ 298 }; \ 299 static void pc_machine_init_##suffix(void) \ 300 { \ 301 type_register(&pc_machine_type_##suffix); \ 302 } \ 303 type_init(pc_machine_init_##suffix) 304 305 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); 306 #endif 307