1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "exec/memory.h" 5 #include "hw/boards.h" 6 #include "hw/isa/isa.h" 7 #include "hw/block/fdc.h" 8 #include "hw/block/flash.h" 9 #include "net/net.h" 10 #include "hw/i386/ioapic.h" 11 12 #include "qemu/range.h" 13 #include "qemu/bitmap.h" 14 #include "qemu/module.h" 15 #include "hw/pci/pci.h" 16 #include "hw/mem/pc-dimm.h" 17 #include "hw/mem/nvdimm.h" 18 #include "hw/acpi/acpi_dev_interface.h" 19 20 #define HPET_INTCAP "hpet-intcap" 21 22 /** 23 * PCMachineState: 24 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 25 * @boot_cpus: number of present VCPUs 26 * @smp_dies: number of dies per one package 27 */ 28 struct PCMachineState { 29 /*< private >*/ 30 MachineState parent_obj; 31 32 /* <public> */ 33 34 /* State for other subsystems/APIs: */ 35 Notifier machine_done; 36 37 /* Pointers to devices and objects: */ 38 HotplugHandler *acpi_dev; 39 ISADevice *rtc; 40 PCIBus *bus; 41 I2CBus *smbus; 42 FWCfgState *fw_cfg; 43 qemu_irq *gsi; 44 PFlashCFI01 *flash[2]; 45 GMappedFile *initrd_mapped_file; 46 47 /* Configuration options: */ 48 uint64_t max_ram_below_4g; 49 OnOffAuto vmport; 50 OnOffAuto smm; 51 52 bool acpi_build_enabled; 53 bool smbus_enabled; 54 bool sata_enabled; 55 bool pit_enabled; 56 57 /* RAM information (sizes, addresses, configuration): */ 58 ram_addr_t below_4g_mem_size, above_4g_mem_size; 59 60 /* CPU and apic information: */ 61 bool apic_xrupt_override; 62 unsigned apic_id_limit; 63 uint16_t boot_cpus; 64 unsigned smp_dies; 65 66 /* NUMA information: */ 67 uint64_t numa_nodes; 68 uint64_t *node_mem; 69 70 /* Address space used by IOAPIC device. All IOAPIC interrupts 71 * will be translated to MSI messages in the address space. */ 72 AddressSpace *ioapic_as; 73 74 /* ACPI Memory hotplug IO base address */ 75 hwaddr memhp_io_base; 76 }; 77 78 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 79 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" 80 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 81 #define PC_MACHINE_VMPORT "vmport" 82 #define PC_MACHINE_SMM "smm" 83 #define PC_MACHINE_SMBUS "smbus" 84 #define PC_MACHINE_SATA "sata" 85 #define PC_MACHINE_PIT "pit" 86 87 /** 88 * PCMachineClass: 89 * 90 * Compat fields: 91 * 92 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 93 * backend's alignment value if provided 94 * @acpi_data_size: Size of the chunk of memory at the top of RAM 95 * for the BIOS ACPI tables and other BIOS 96 * datastructures. 97 * @gigabyte_align: Make sure that guest addresses aligned at 98 * 1Gbyte boundaries get mapped to host 99 * addresses aligned at 1Gbyte boundaries. This 100 * way we can use 1GByte pages in the host. 101 * 102 */ 103 typedef struct PCMachineClass { 104 /*< private >*/ 105 MachineClass parent_class; 106 107 /*< public >*/ 108 109 /* Device configuration: */ 110 bool pci_enabled; 111 bool kvmclock_enabled; 112 const char *default_nic_model; 113 114 /* Compat options: */ 115 116 /* Default CPU model version. See x86_cpu_set_default_version(). */ 117 int default_cpu_version; 118 119 /* ACPI compat: */ 120 bool has_acpi_build; 121 bool rsdp_in_ram; 122 int legacy_acpi_table_size; 123 unsigned acpi_data_size; 124 bool do_not_add_smb_acpi; 125 126 /* SMBIOS compat: */ 127 bool smbios_defaults; 128 bool smbios_legacy_mode; 129 bool smbios_uuid_encoded; 130 131 /* RAM / address space compat: */ 132 bool gigabyte_align; 133 bool has_reserved_memory; 134 bool enforce_aligned_dimm; 135 bool broken_reserved_end; 136 137 /* TSC rate migration: */ 138 bool save_tsc_khz; 139 /* generate legacy CPU hotplug AML */ 140 bool legacy_cpu_hotplug; 141 142 /* use DMA capable linuxboot option rom */ 143 bool linuxboot_dma_enabled; 144 145 /* use PVH to load kernels that support this feature */ 146 bool pvh_enabled; 147 148 /* Enables contiguous-apic-ID mode */ 149 bool compat_apic_id_mode; 150 } PCMachineClass; 151 152 #define TYPE_PC_MACHINE "generic-pc-machine" 153 #define PC_MACHINE(obj) \ 154 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE) 155 #define PC_MACHINE_GET_CLASS(obj) \ 156 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE) 157 #define PC_MACHINE_CLASS(klass) \ 158 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) 159 160 /* i8259.c */ 161 162 extern DeviceState *isa_pic; 163 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); 164 qemu_irq *kvm_i8259_init(ISABus *bus); 165 int pic_read_irq(DeviceState *d); 166 int pic_get_output(DeviceState *d); 167 168 /* ioapic.c */ 169 170 /* Global System Interrupts */ 171 172 #define GSI_NUM_PINS IOAPIC_NUM_PINS 173 174 typedef struct GSIState { 175 qemu_irq i8259_irq[ISA_NUM_IRQS]; 176 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 177 } GSIState; 178 179 void gsi_handler(void *opaque, int n, int level); 180 181 /* vmport.c */ 182 #define TYPE_VMPORT "vmport" 183 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); 184 185 static inline void vmport_init(ISABus *bus) 186 { 187 isa_create_simple(bus, TYPE_VMPORT); 188 } 189 190 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); 191 void vmmouse_get_data(uint32_t *data); 192 void vmmouse_set_data(const uint32_t *data); 193 194 /* pc.c */ 195 extern int fd_bootchk; 196 197 bool pc_machine_is_smm_enabled(PCMachineState *pcms); 198 void pc_register_ferr_irq(qemu_irq irq); 199 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 200 201 void pc_cpus_init(PCMachineState *pcms); 202 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp); 203 void pc_smp_parse(MachineState *ms, QemuOpts *opts); 204 205 void pc_guest_info_init(PCMachineState *pcms); 206 207 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 208 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 209 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 210 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 211 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 212 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 213 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 214 215 216 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 217 MemoryRegion *pci_address_space); 218 219 void xen_load_linux(PCMachineState *pcms); 220 void pc_memory_init(PCMachineState *pcms, 221 MemoryRegion *system_memory, 222 MemoryRegion *rom_memory, 223 MemoryRegion **ram_memory); 224 uint64_t pc_pci_hole64_start(void); 225 qemu_irq pc_allocate_cpu_irq(void); 226 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 227 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 228 ISADevice **rtc_state, 229 bool create_fdctrl, 230 bool no_vmport, 231 bool has_pit, 232 uint32_t hpet_irqs); 233 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 234 void pc_cmos_init(PCMachineState *pcms, 235 BusState *ide0, BusState *ide1, 236 ISADevice *s); 237 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 238 void pc_pci_device_init(PCIBus *pci_bus); 239 240 typedef void (*cpu_set_smm_t)(int smm, void *arg); 241 242 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 243 244 ISADevice *pc_find_fdc0(void); 245 int cmos_get_fd_drive_type(FloppyDriveType fd0); 246 247 #define FW_CFG_IO_BASE 0x510 248 249 #define PORT92_A20_LINE "a20" 250 251 /* acpi_piix.c */ 252 253 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 254 qemu_irq sci_irq, qemu_irq smi_irq, 255 int smm_enabled, DeviceState **piix4_pm); 256 257 /* hpet.c */ 258 extern int no_hpet; 259 260 /* piix_pci.c */ 261 struct PCII440FXState; 262 typedef struct PCII440FXState PCII440FXState; 263 264 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" 265 #define TYPE_I440FX_PCI_DEVICE "i440FX" 266 267 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" 268 269 /* 270 * Reset Control Register: PCI-accessible ISA-Compatible Register at address 271 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 272 */ 273 #define RCR_IOPORT 0xcf9 274 275 PCIBus *i440fx_init(const char *host_type, const char *pci_type, 276 PCII440FXState **pi440fx_state, int *piix_devfn, 277 ISABus **isa_bus, qemu_irq *pic, 278 MemoryRegion *address_space_mem, 279 MemoryRegion *address_space_io, 280 ram_addr_t ram_size, 281 ram_addr_t below_4g_mem_size, 282 ram_addr_t above_4g_mem_size, 283 MemoryRegion *pci_memory, 284 MemoryRegion *ram_memory); 285 286 PCIBus *find_i440fx(void); 287 /* piix4.c */ 288 extern PCIDevice *piix4_dev; 289 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); 290 291 /* pc_sysfw.c */ 292 void pc_system_flash_create(PCMachineState *pcms); 293 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 294 295 /* acpi-build.c */ 296 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 297 const CPUArchIdList *apic_ids, GArray *entry); 298 299 extern GlobalProperty pc_compat_4_1[]; 300 extern const size_t pc_compat_4_1_len; 301 302 extern GlobalProperty pc_compat_4_0[]; 303 extern const size_t pc_compat_4_0_len; 304 305 extern GlobalProperty pc_compat_3_1[]; 306 extern const size_t pc_compat_3_1_len; 307 308 extern GlobalProperty pc_compat_3_0[]; 309 extern const size_t pc_compat_3_0_len; 310 311 extern GlobalProperty pc_compat_2_12[]; 312 extern const size_t pc_compat_2_12_len; 313 314 extern GlobalProperty pc_compat_2_11[]; 315 extern const size_t pc_compat_2_11_len; 316 317 extern GlobalProperty pc_compat_2_10[]; 318 extern const size_t pc_compat_2_10_len; 319 320 extern GlobalProperty pc_compat_2_9[]; 321 extern const size_t pc_compat_2_9_len; 322 323 extern GlobalProperty pc_compat_2_8[]; 324 extern const size_t pc_compat_2_8_len; 325 326 extern GlobalProperty pc_compat_2_7[]; 327 extern const size_t pc_compat_2_7_len; 328 329 extern GlobalProperty pc_compat_2_6[]; 330 extern const size_t pc_compat_2_6_len; 331 332 extern GlobalProperty pc_compat_2_5[]; 333 extern const size_t pc_compat_2_5_len; 334 335 extern GlobalProperty pc_compat_2_4[]; 336 extern const size_t pc_compat_2_4_len; 337 338 extern GlobalProperty pc_compat_2_3[]; 339 extern const size_t pc_compat_2_3_len; 340 341 extern GlobalProperty pc_compat_2_2[]; 342 extern const size_t pc_compat_2_2_len; 343 344 extern GlobalProperty pc_compat_2_1[]; 345 extern const size_t pc_compat_2_1_len; 346 347 extern GlobalProperty pc_compat_2_0[]; 348 extern const size_t pc_compat_2_0_len; 349 350 extern GlobalProperty pc_compat_1_7[]; 351 extern const size_t pc_compat_1_7_len; 352 353 extern GlobalProperty pc_compat_1_6[]; 354 extern const size_t pc_compat_1_6_len; 355 356 extern GlobalProperty pc_compat_1_5[]; 357 extern const size_t pc_compat_1_5_len; 358 359 extern GlobalProperty pc_compat_1_4[]; 360 extern const size_t pc_compat_1_4_len; 361 362 /* Helper for setting model-id for CPU models that changed model-id 363 * depending on QEMU versions up to QEMU 2.4. 364 */ 365 #define PC_CPU_MODEL_IDS(v) \ 366 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 367 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 368 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 369 370 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 371 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 372 { \ 373 MachineClass *mc = MACHINE_CLASS(oc); \ 374 optsfn(mc); \ 375 mc->init = initfn; \ 376 } \ 377 static const TypeInfo pc_machine_type_##suffix = { \ 378 .name = namestr TYPE_MACHINE_SUFFIX, \ 379 .parent = TYPE_PC_MACHINE, \ 380 .class_init = pc_machine_##suffix##_class_init, \ 381 }; \ 382 static void pc_machine_init_##suffix(void) \ 383 { \ 384 type_register(&pc_machine_type_##suffix); \ 385 } \ 386 type_init(pc_machine_init_##suffix) 387 388 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); 389 #endif 390