1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu/notify.h" 5 #include "qapi/qapi-types-common.h" 6 #include "qemu/uuid.h" 7 #include "hw/boards.h" 8 #include "hw/block/fdc.h" 9 #include "hw/block/flash.h" 10 #include "hw/i386/x86.h" 11 12 #include "hw/acpi/acpi_dev_interface.h" 13 #include "hw/hotplug.h" 14 #include "qom/object.h" 15 16 #define HPET_INTCAP "hpet-intcap" 17 18 /** 19 * PCMachineState: 20 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 21 * @boot_cpus: number of present VCPUs 22 */ 23 typedef struct PCMachineState { 24 /*< private >*/ 25 X86MachineState parent_obj; 26 27 /* <public> */ 28 29 /* State for other subsystems/APIs: */ 30 Notifier machine_done; 31 32 /* Pointers to devices and objects: */ 33 PCIBus *bus; 34 I2CBus *smbus; 35 PFlashCFI01 *flash[2]; 36 ISADevice *pcspk; 37 38 /* Configuration options: */ 39 uint64_t max_ram_below_4g; 40 OnOffAuto vmport; 41 42 bool acpi_build_enabled; 43 bool smbus_enabled; 44 bool sata_enabled; 45 bool pit_enabled; 46 bool hpet_enabled; 47 bool default_bus_bypass_iommu; 48 uint64_t max_fw_size; 49 50 /* NUMA information: */ 51 uint64_t numa_nodes; 52 uint64_t *node_mem; 53 54 /* ACPI Memory hotplug IO base address */ 55 hwaddr memhp_io_base; 56 } PCMachineState; 57 58 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 59 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 60 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" 61 #define PC_MACHINE_VMPORT "vmport" 62 #define PC_MACHINE_SMBUS "smbus" 63 #define PC_MACHINE_SATA "sata" 64 #define PC_MACHINE_PIT "pit" 65 #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" 66 /** 67 * PCMachineClass: 68 * 69 * Compat fields: 70 * 71 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 72 * backend's alignment value if provided 73 * @acpi_data_size: Size of the chunk of memory at the top of RAM 74 * for the BIOS ACPI tables and other BIOS 75 * datastructures. 76 * @gigabyte_align: Make sure that guest addresses aligned at 77 * 1Gbyte boundaries get mapped to host 78 * addresses aligned at 1Gbyte boundaries. This 79 * way we can use 1GByte pages in the host. 80 * 81 */ 82 struct PCMachineClass { 83 /*< private >*/ 84 X86MachineClass parent_class; 85 86 /*< public >*/ 87 88 /* Device configuration: */ 89 bool pci_enabled; 90 bool kvmclock_enabled; 91 const char *default_nic_model; 92 93 /* Compat options: */ 94 95 /* Default CPU model version. See x86_cpu_set_default_version(). */ 96 int default_cpu_version; 97 98 /* ACPI compat: */ 99 bool has_acpi_build; 100 bool rsdp_in_ram; 101 int legacy_acpi_table_size; 102 unsigned acpi_data_size; 103 bool do_not_add_smb_acpi; 104 int pci_root_uid; 105 106 /* SMBIOS compat: */ 107 bool smbios_defaults; 108 bool smbios_legacy_mode; 109 bool smbios_uuid_encoded; 110 111 /* RAM / address space compat: */ 112 bool gigabyte_align; 113 bool has_reserved_memory; 114 bool enforce_aligned_dimm; 115 bool broken_reserved_end; 116 117 /* generate legacy CPU hotplug AML */ 118 bool legacy_cpu_hotplug; 119 120 /* use DMA capable linuxboot option rom */ 121 bool linuxboot_dma_enabled; 122 123 /* use PVH to load kernels that support this feature */ 124 bool pvh_enabled; 125 126 /* create kvmclock device even when KVM PV features are not exposed */ 127 bool kvmclock_create_always; 128 }; 129 130 #define TYPE_PC_MACHINE "generic-pc-machine" 131 OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE) 132 133 /* ioapic.c */ 134 135 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled); 136 137 /* pc.c */ 138 extern int fd_bootchk; 139 140 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 141 142 void pc_guest_info_init(PCMachineState *pcms); 143 144 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 145 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 146 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 147 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 148 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 149 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 150 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 151 152 153 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 154 MemoryRegion *pci_address_space); 155 156 void xen_load_linux(PCMachineState *pcms); 157 void pc_memory_init(PCMachineState *pcms, 158 MemoryRegion *system_memory, 159 MemoryRegion *rom_memory, 160 MemoryRegion **ram_memory); 161 uint64_t pc_pci_hole64_start(void); 162 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 163 void pc_basic_device_init(struct PCMachineState *pcms, 164 ISABus *isa_bus, qemu_irq *gsi, 165 ISADevice **rtc_state, 166 bool create_fdctrl, 167 uint32_t hpet_irqs); 168 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 169 void pc_cmos_init(PCMachineState *pcms, 170 BusState *ide0, BusState *ide1, 171 ISADevice *s); 172 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 173 void pc_pci_device_init(PCIBus *pci_bus); 174 175 typedef void (*cpu_set_smm_t)(int smm, void *arg); 176 177 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs); 178 179 ISADevice *pc_find_fdc0(void); 180 181 /* port92.c */ 182 #define PORT92_A20_LINE "a20" 183 184 #define TYPE_PORT92 "port92" 185 186 /* pc_sysfw.c */ 187 void pc_system_flash_create(PCMachineState *pcms); 188 void pc_system_flash_cleanup_unused(PCMachineState *pcms); 189 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 190 bool pc_system_ovmf_table_find(const char *entry, uint8_t **data, 191 int *data_len); 192 void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size); 193 194 195 /* acpi-build.c */ 196 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 197 const CPUArchIdList *apic_ids, GArray *entry); 198 199 extern GlobalProperty pc_compat_6_0[]; 200 extern const size_t pc_compat_6_0_len; 201 202 extern GlobalProperty pc_compat_5_2[]; 203 extern const size_t pc_compat_5_2_len; 204 205 extern GlobalProperty pc_compat_5_1[]; 206 extern const size_t pc_compat_5_1_len; 207 208 extern GlobalProperty pc_compat_5_0[]; 209 extern const size_t pc_compat_5_0_len; 210 211 extern GlobalProperty pc_compat_4_2[]; 212 extern const size_t pc_compat_4_2_len; 213 214 extern GlobalProperty pc_compat_4_1[]; 215 extern const size_t pc_compat_4_1_len; 216 217 extern GlobalProperty pc_compat_4_0[]; 218 extern const size_t pc_compat_4_0_len; 219 220 extern GlobalProperty pc_compat_3_1[]; 221 extern const size_t pc_compat_3_1_len; 222 223 extern GlobalProperty pc_compat_3_0[]; 224 extern const size_t pc_compat_3_0_len; 225 226 extern GlobalProperty pc_compat_2_12[]; 227 extern const size_t pc_compat_2_12_len; 228 229 extern GlobalProperty pc_compat_2_11[]; 230 extern const size_t pc_compat_2_11_len; 231 232 extern GlobalProperty pc_compat_2_10[]; 233 extern const size_t pc_compat_2_10_len; 234 235 extern GlobalProperty pc_compat_2_9[]; 236 extern const size_t pc_compat_2_9_len; 237 238 extern GlobalProperty pc_compat_2_8[]; 239 extern const size_t pc_compat_2_8_len; 240 241 extern GlobalProperty pc_compat_2_7[]; 242 extern const size_t pc_compat_2_7_len; 243 244 extern GlobalProperty pc_compat_2_6[]; 245 extern const size_t pc_compat_2_6_len; 246 247 extern GlobalProperty pc_compat_2_5[]; 248 extern const size_t pc_compat_2_5_len; 249 250 extern GlobalProperty pc_compat_2_4[]; 251 extern const size_t pc_compat_2_4_len; 252 253 extern GlobalProperty pc_compat_2_3[]; 254 extern const size_t pc_compat_2_3_len; 255 256 extern GlobalProperty pc_compat_2_2[]; 257 extern const size_t pc_compat_2_2_len; 258 259 extern GlobalProperty pc_compat_2_1[]; 260 extern const size_t pc_compat_2_1_len; 261 262 extern GlobalProperty pc_compat_2_0[]; 263 extern const size_t pc_compat_2_0_len; 264 265 extern GlobalProperty pc_compat_1_7[]; 266 extern const size_t pc_compat_1_7_len; 267 268 extern GlobalProperty pc_compat_1_6[]; 269 extern const size_t pc_compat_1_6_len; 270 271 extern GlobalProperty pc_compat_1_5[]; 272 extern const size_t pc_compat_1_5_len; 273 274 extern GlobalProperty pc_compat_1_4[]; 275 extern const size_t pc_compat_1_4_len; 276 277 /* Helper for setting model-id for CPU models that changed model-id 278 * depending on QEMU versions up to QEMU 2.4. 279 */ 280 #define PC_CPU_MODEL_IDS(v) \ 281 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 282 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 283 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 284 285 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 286 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 287 { \ 288 MachineClass *mc = MACHINE_CLASS(oc); \ 289 optsfn(mc); \ 290 mc->init = initfn; \ 291 } \ 292 static const TypeInfo pc_machine_type_##suffix = { \ 293 .name = namestr TYPE_MACHINE_SUFFIX, \ 294 .parent = TYPE_PC_MACHINE, \ 295 .class_init = pc_machine_##suffix##_class_init, \ 296 }; \ 297 static void pc_machine_init_##suffix(void) \ 298 { \ 299 type_register(&pc_machine_type_##suffix); \ 300 } \ 301 type_init(pc_machine_init_##suffix) 302 303 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); 304 #endif 305