1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu-common.h" 5 #include "exec/memory.h" 6 #include "hw/isa/isa.h" 7 #include "hw/block/fdc.h" 8 #include "net/net.h" 9 #include "hw/i386/ioapic.h" 10 11 /* PC-style peripherals (also used by other machines). */ 12 13 /* parallel.c */ 14 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr) 15 { 16 DeviceState *dev; 17 ISADevice *isadev; 18 19 isadev = isa_try_create(bus, "isa-parallel"); 20 if (!isadev) { 21 return false; 22 } 23 dev = DEVICE(isadev); 24 qdev_prop_set_uint32(dev, "index", index); 25 qdev_prop_set_chr(dev, "chardev", chr); 26 if (qdev_init(dev) < 0) { 27 return false; 28 } 29 return true; 30 } 31 32 bool parallel_mm_init(MemoryRegion *address_space, 33 hwaddr base, int it_shift, qemu_irq irq, 34 CharDriverState *chr); 35 36 /* i8259.c */ 37 38 extern DeviceState *isa_pic; 39 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); 40 qemu_irq *kvm_i8259_init(ISABus *bus); 41 int pic_read_irq(DeviceState *d); 42 int pic_get_output(DeviceState *d); 43 void pic_info(Monitor *mon, const QDict *qdict); 44 void irq_info(Monitor *mon, const QDict *qdict); 45 46 /* Global System Interrupts */ 47 48 #define GSI_NUM_PINS IOAPIC_NUM_PINS 49 50 typedef struct GSIState { 51 qemu_irq i8259_irq[ISA_NUM_IRQS]; 52 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 53 } GSIState; 54 55 void gsi_handler(void *opaque, int n, int level); 56 57 /* vmport.c */ 58 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); 59 60 static inline void vmport_init(ISABus *bus) 61 { 62 isa_create_simple(bus, "vmport"); 63 } 64 65 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); 66 void vmmouse_get_data(uint32_t *data); 67 void vmmouse_set_data(const uint32_t *data); 68 69 /* pckbd.c */ 70 71 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); 72 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 73 MemoryRegion *region, ram_addr_t size, 74 hwaddr mask); 75 void i8042_isa_mouse_fake_event(void *opaque); 76 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out); 77 78 /* pc.c */ 79 extern int fd_bootchk; 80 81 void pc_register_ferr_irq(qemu_irq irq); 82 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 83 84 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge); 85 void pc_hot_add_cpu(const int64_t id, Error **errp); 86 void pc_acpi_init(const char *default_dsdt); 87 FWCfgState *pc_memory_init(MemoryRegion *system_memory, 88 const char *kernel_filename, 89 const char *kernel_cmdline, 90 const char *initrd_filename, 91 ram_addr_t below_4g_mem_size, 92 ram_addr_t above_4g_mem_size, 93 MemoryRegion *rom_memory, 94 MemoryRegion **ram_memory); 95 qemu_irq *pc_allocate_cpu_irq(void); 96 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 97 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 98 ISADevice **rtc_state, 99 ISADevice **floppy, 100 bool no_vmport); 101 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 102 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 103 const char *boot_device, 104 ISADevice *floppy, BusState *ide0, BusState *ide1, 105 ISADevice *s); 106 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus); 107 void pc_pci_device_init(PCIBus *pci_bus); 108 109 typedef void (*cpu_set_smm_t)(int smm, void *arg); 110 void cpu_smm_register(cpu_set_smm_t callback, void *arg); 111 112 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 113 114 /* acpi_piix.c */ 115 116 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 117 qemu_irq sci_irq, qemu_irq smi_irq, 118 int kvm_enabled, FWCfgState *fw_cfg); 119 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); 120 121 /* hpet.c */ 122 extern int no_hpet; 123 124 /* piix_pci.c */ 125 struct PCII440FXState; 126 typedef struct PCII440FXState PCII440FXState; 127 128 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, 129 ISABus **isa_bus, qemu_irq *pic, 130 MemoryRegion *address_space_mem, 131 MemoryRegion *address_space_io, 132 ram_addr_t ram_size, 133 hwaddr pci_hole_start, 134 hwaddr pci_hole_size, 135 hwaddr pci_hole64_start, 136 hwaddr pci_hole64_size, 137 MemoryRegion *pci_memory, 138 MemoryRegion *ram_memory); 139 140 /* piix4.c */ 141 extern PCIDevice *piix4_dev; 142 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); 143 144 /* vga.c */ 145 enum vga_retrace_method { 146 VGA_RETRACE_DUMB, 147 VGA_RETRACE_PRECISE 148 }; 149 150 extern enum vga_retrace_method vga_retrace_method; 151 152 int isa_vga_mm_init(hwaddr vram_base, 153 hwaddr ctrl_base, int it_shift, 154 MemoryRegion *address_space); 155 156 /* ne2000.c */ 157 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) 158 { 159 DeviceState *dev; 160 ISADevice *isadev; 161 162 qemu_check_nic_model(nd, "ne2k_isa"); 163 164 isadev = isa_try_create(bus, "ne2k_isa"); 165 if (!isadev) { 166 return false; 167 } 168 dev = DEVICE(isadev); 169 qdev_prop_set_uint32(dev, "iobase", base); 170 qdev_prop_set_uint32(dev, "irq", irq); 171 qdev_set_nic_properties(dev, nd); 172 qdev_init_nofail(dev); 173 return true; 174 } 175 176 /* pc_sysfw.c */ 177 void pc_system_firmware_init(MemoryRegion *rom_memory); 178 179 /* pvpanic.c */ 180 int pvpanic_init(ISABus *bus); 181 182 /* e820 types */ 183 #define E820_RAM 1 184 #define E820_RESERVED 2 185 #define E820_ACPI 3 186 #define E820_NVS 4 187 #define E820_UNUSABLE 5 188 189 int e820_add_entry(uint64_t, uint64_t, uint32_t); 190 191 #define PC_COMPAT_1_5 \ 192 {\ 193 .driver = "Conroe-" TYPE_X86_CPU,\ 194 .property = "model",\ 195 .value = stringify(2),\ 196 },{\ 197 .driver = "Conroe-" TYPE_X86_CPU,\ 198 .property = "level",\ 199 .value = stringify(2),\ 200 },{\ 201 .driver = "Penryn-" TYPE_X86_CPU,\ 202 .property = "model",\ 203 .value = stringify(2),\ 204 },{\ 205 .driver = "Penryn-" TYPE_X86_CPU,\ 206 .property = "level",\ 207 .value = stringify(2),\ 208 },{\ 209 .driver = "Nehalem-" TYPE_X86_CPU,\ 210 .property = "model",\ 211 .value = stringify(2),\ 212 },{\ 213 .driver = "Nehalem-" TYPE_X86_CPU,\ 214 .property = "level",\ 215 .value = stringify(2),\ 216 } 217 218 #define PC_COMPAT_1_4 \ 219 PC_COMPAT_1_5, \ 220 {\ 221 .driver = "scsi-hd",\ 222 .property = "discard_granularity",\ 223 .value = stringify(0),\ 224 },{\ 225 .driver = "scsi-cd",\ 226 .property = "discard_granularity",\ 227 .value = stringify(0),\ 228 },{\ 229 .driver = "scsi-disk",\ 230 .property = "discard_granularity",\ 231 .value = stringify(0),\ 232 },{\ 233 .driver = "ide-hd",\ 234 .property = "discard_granularity",\ 235 .value = stringify(0),\ 236 },{\ 237 .driver = "ide-cd",\ 238 .property = "discard_granularity",\ 239 .value = stringify(0),\ 240 },{\ 241 .driver = "ide-drive",\ 242 .property = "discard_granularity",\ 243 .value = stringify(0),\ 244 },{\ 245 .driver = "virtio-blk-pci",\ 246 .property = "discard_granularity",\ 247 .value = stringify(0),\ 248 },{\ 249 .driver = "virtio-serial-pci",\ 250 .property = "vectors",\ 251 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\ 252 .value = stringify(0xFFFFFFFF),\ 253 },{ \ 254 .driver = "virtio-net-pci", \ 255 .property = "ctrl_guest_offloads", \ 256 .value = "off", \ 257 },{\ 258 .driver = "e1000",\ 259 .property = "romfile",\ 260 .value = "pxe-e1000.rom",\ 261 },{\ 262 .driver = "ne2k_pci",\ 263 .property = "romfile",\ 264 .value = "pxe-ne2k_pci.rom",\ 265 },{\ 266 .driver = "pcnet",\ 267 .property = "romfile",\ 268 .value = "pxe-pcnet.rom",\ 269 },{\ 270 .driver = "rtl8139",\ 271 .property = "romfile",\ 272 .value = "pxe-rtl8139.rom",\ 273 },{\ 274 .driver = "virtio-net-pci",\ 275 .property = "romfile",\ 276 .value = "pxe-virtio.rom",\ 277 },{\ 278 .driver = "486-" TYPE_X86_CPU,\ 279 .property = "model",\ 280 .value = stringify(0),\ 281 } 282 283 #endif 284