1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu/notify.h" 5 #include "qapi/qapi-types-common.h" 6 #include "qemu/uuid.h" 7 #include "hw/boards.h" 8 #include "hw/block/fdc.h" 9 #include "hw/block/flash.h" 10 #include "hw/i386/x86.h" 11 12 #include "hw/hotplug.h" 13 #include "qom/object.h" 14 #include "hw/i386/sgx-epc.h" 15 #include "hw/cxl/cxl.h" 16 17 #define MAX_IDE_BUS 2 18 19 /** 20 * PCMachineState: 21 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 22 * @boot_cpus: number of present VCPUs 23 */ 24 typedef struct PCMachineState { 25 /*< private >*/ 26 X86MachineState parent_obj; 27 28 /* <public> */ 29 30 /* State for other subsystems/APIs: */ 31 Notifier machine_done; 32 33 /* Pointers to devices and objects: */ 34 PCIBus *pcibus; 35 I2CBus *smbus; 36 PFlashCFI01 *flash[2]; 37 ISADevice *pcspk; 38 DeviceState *iommu; 39 BusState *idebus[MAX_IDE_BUS]; 40 41 /* Configuration options: */ 42 uint64_t max_ram_below_4g; 43 OnOffAuto vmport; 44 SmbiosEntryPointType smbios_entry_point_type; 45 const char *south_bridge; 46 47 bool acpi_build_enabled; 48 bool smbus_enabled; 49 bool sata_enabled; 50 bool hpet_enabled; 51 bool i8042_enabled; 52 bool default_bus_bypass_iommu; 53 uint64_t max_fw_size; 54 55 /* ACPI Memory hotplug IO base address */ 56 hwaddr memhp_io_base; 57 58 SGXEPCState sgx_epc; 59 CXLState cxl_devices_state; 60 } PCMachineState; 61 62 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 63 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 64 #define PC_MACHINE_VMPORT "vmport" 65 #define PC_MACHINE_SMBUS "smbus" 66 #define PC_MACHINE_SATA "sata" 67 #define PC_MACHINE_I8042 "i8042" 68 #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" 69 #define PC_MACHINE_SMBIOS_EP "smbios-entry-point-type" 70 71 /** 72 * PCMachineClass: 73 * 74 * Compat fields: 75 * 76 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 77 * backend's alignment value if provided 78 * @acpi_data_size: Size of the chunk of memory at the top of RAM 79 * for the BIOS ACPI tables and other BIOS 80 * datastructures. 81 * @gigabyte_align: Make sure that guest addresses aligned at 82 * 1Gbyte boundaries get mapped to host 83 * addresses aligned at 1Gbyte boundaries. This 84 * way we can use 1GByte pages in the host. 85 * 86 */ 87 struct PCMachineClass { 88 /*< private >*/ 89 X86MachineClass parent_class; 90 91 /*< public >*/ 92 93 /* Device configuration: */ 94 bool pci_enabled; 95 const char *default_south_bridge; 96 97 /* Compat options: */ 98 99 /* Default CPU model version. See x86_cpu_set_default_version(). */ 100 int default_cpu_version; 101 102 /* ACPI compat: */ 103 bool has_acpi_build; 104 bool rsdp_in_ram; 105 int legacy_acpi_table_size; 106 unsigned acpi_data_size; 107 int pci_root_uid; 108 109 /* SMBIOS compat: */ 110 bool smbios_defaults; 111 bool smbios_legacy_mode; 112 bool smbios_uuid_encoded; 113 SmbiosEntryPointType default_smbios_ep_type; 114 115 /* RAM / address space compat: */ 116 bool gigabyte_align; 117 bool has_reserved_memory; 118 bool enforce_aligned_dimm; 119 bool broken_reserved_end; 120 bool enforce_amd_1tb_hole; 121 122 /* generate legacy CPU hotplug AML */ 123 bool legacy_cpu_hotplug; 124 125 /* use PVH to load kernels that support this feature */ 126 bool pvh_enabled; 127 128 /* create kvmclock device even when KVM PV features are not exposed */ 129 bool kvmclock_create_always; 130 131 /* resizable acpi blob compat */ 132 bool resizable_acpi_blob; 133 134 /* 135 * whether the machine type implements broken 32-bit address space bound 136 * check for memory. 137 */ 138 bool broken_32bit_mem_addr_check; 139 }; 140 141 #define TYPE_PC_MACHINE "generic-pc-machine" 142 OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE) 143 144 /* ioapic.c */ 145 146 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled); 147 148 /* pc.c */ 149 extern int fd_bootchk; 150 151 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 152 153 #define PCI_HOST_PROP_RAM_MEM "ram-mem" 154 #define PCI_HOST_PROP_PCI_MEM "pci-mem" 155 #define PCI_HOST_PROP_SYSTEM_MEM "system-mem" 156 #define PCI_HOST_PROP_IO_MEM "io-mem" 157 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 158 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 159 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 160 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 161 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 162 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 163 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 164 165 166 void pc_pci_as_mapping_init(MemoryRegion *system_memory, 167 MemoryRegion *pci_address_space); 168 169 void xen_load_linux(PCMachineState *pcms); 170 void pc_memory_init(PCMachineState *pcms, 171 MemoryRegion *system_memory, 172 MemoryRegion *rom_memory, 173 uint64_t pci_hole64_size); 174 uint64_t pc_pci_hole64_start(void); 175 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 176 void pc_basic_device_init(struct PCMachineState *pcms, 177 ISABus *isa_bus, qemu_irq *gsi, 178 ISADevice *rtc_state, 179 bool create_fdctrl, 180 uint32_t hpet_irqs); 181 void pc_cmos_init(PCMachineState *pcms, 182 ISADevice *s); 183 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 184 185 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs); 186 187 /* port92.c */ 188 #define PORT92_A20_LINE "a20" 189 190 #define TYPE_PORT92 "port92" 191 192 /* pc_sysfw.c */ 193 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 194 bool pc_system_ovmf_table_find(const char *entry, uint8_t **data, 195 int *data_len); 196 void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size); 197 198 /* sgx.c */ 199 void pc_machine_init_sgx_epc(PCMachineState *pcms); 200 201 extern GlobalProperty pc_compat_8_2[]; 202 extern const size_t pc_compat_8_2_len; 203 204 extern GlobalProperty pc_compat_8_1[]; 205 extern const size_t pc_compat_8_1_len; 206 207 extern GlobalProperty pc_compat_8_0[]; 208 extern const size_t pc_compat_8_0_len; 209 210 extern GlobalProperty pc_compat_7_2[]; 211 extern const size_t pc_compat_7_2_len; 212 213 extern GlobalProperty pc_compat_7_1[]; 214 extern const size_t pc_compat_7_1_len; 215 216 extern GlobalProperty pc_compat_7_0[]; 217 extern const size_t pc_compat_7_0_len; 218 219 extern GlobalProperty pc_compat_6_2[]; 220 extern const size_t pc_compat_6_2_len; 221 222 extern GlobalProperty pc_compat_6_1[]; 223 extern const size_t pc_compat_6_1_len; 224 225 extern GlobalProperty pc_compat_6_0[]; 226 extern const size_t pc_compat_6_0_len; 227 228 extern GlobalProperty pc_compat_5_2[]; 229 extern const size_t pc_compat_5_2_len; 230 231 extern GlobalProperty pc_compat_5_1[]; 232 extern const size_t pc_compat_5_1_len; 233 234 extern GlobalProperty pc_compat_5_0[]; 235 extern const size_t pc_compat_5_0_len; 236 237 extern GlobalProperty pc_compat_4_2[]; 238 extern const size_t pc_compat_4_2_len; 239 240 extern GlobalProperty pc_compat_4_1[]; 241 extern const size_t pc_compat_4_1_len; 242 243 extern GlobalProperty pc_compat_4_0[]; 244 extern const size_t pc_compat_4_0_len; 245 246 extern GlobalProperty pc_compat_3_1[]; 247 extern const size_t pc_compat_3_1_len; 248 249 extern GlobalProperty pc_compat_3_0[]; 250 extern const size_t pc_compat_3_0_len; 251 252 extern GlobalProperty pc_compat_2_12[]; 253 extern const size_t pc_compat_2_12_len; 254 255 extern GlobalProperty pc_compat_2_11[]; 256 extern const size_t pc_compat_2_11_len; 257 258 extern GlobalProperty pc_compat_2_10[]; 259 extern const size_t pc_compat_2_10_len; 260 261 extern GlobalProperty pc_compat_2_9[]; 262 extern const size_t pc_compat_2_9_len; 263 264 extern GlobalProperty pc_compat_2_8[]; 265 extern const size_t pc_compat_2_8_len; 266 267 extern GlobalProperty pc_compat_2_7[]; 268 extern const size_t pc_compat_2_7_len; 269 270 extern GlobalProperty pc_compat_2_6[]; 271 extern const size_t pc_compat_2_6_len; 272 273 extern GlobalProperty pc_compat_2_5[]; 274 extern const size_t pc_compat_2_5_len; 275 276 extern GlobalProperty pc_compat_2_4[]; 277 extern const size_t pc_compat_2_4_len; 278 279 extern GlobalProperty pc_compat_2_3[]; 280 extern const size_t pc_compat_2_3_len; 281 282 extern GlobalProperty pc_compat_2_2[]; 283 extern const size_t pc_compat_2_2_len; 284 285 extern GlobalProperty pc_compat_2_1[]; 286 extern const size_t pc_compat_2_1_len; 287 288 extern GlobalProperty pc_compat_2_0[]; 289 extern const size_t pc_compat_2_0_len; 290 291 extern GlobalProperty pc_compat_1_7[]; 292 extern const size_t pc_compat_1_7_len; 293 294 extern GlobalProperty pc_compat_1_6[]; 295 extern const size_t pc_compat_1_6_len; 296 297 extern GlobalProperty pc_compat_1_5[]; 298 extern const size_t pc_compat_1_5_len; 299 300 extern GlobalProperty pc_compat_1_4[]; 301 extern const size_t pc_compat_1_4_len; 302 303 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 304 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 305 { \ 306 MachineClass *mc = MACHINE_CLASS(oc); \ 307 optsfn(mc); \ 308 mc->init = initfn; \ 309 } \ 310 static const TypeInfo pc_machine_type_##suffix = { \ 311 .name = namestr TYPE_MACHINE_SUFFIX, \ 312 .parent = TYPE_PC_MACHINE, \ 313 .class_init = pc_machine_##suffix##_class_init, \ 314 }; \ 315 static void pc_machine_init_##suffix(void) \ 316 { \ 317 type_register(&pc_machine_type_##suffix); \ 318 } \ 319 type_init(pc_machine_init_##suffix) 320 321 #endif 322