1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "exec/memory.h" 5 #include "hw/boards.h" 6 #include "hw/isa/isa.h" 7 #include "hw/block/fdc.h" 8 #include "hw/block/flash.h" 9 #include "net/net.h" 10 #include "hw/i386/ioapic.h" 11 12 #include "qemu/range.h" 13 #include "qemu/bitmap.h" 14 #include "qemu/module.h" 15 #include "hw/pci/pci.h" 16 #include "hw/mem/pc-dimm.h" 17 #include "hw/mem/nvdimm.h" 18 #include "hw/acpi/acpi_dev_interface.h" 19 20 #define HPET_INTCAP "hpet-intcap" 21 22 /** 23 * PCMachineState: 24 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 25 * @boot_cpus: number of present VCPUs 26 * @smp_dies: number of dies per one package 27 */ 28 struct PCMachineState { 29 /*< private >*/ 30 MachineState parent_obj; 31 32 /* <public> */ 33 34 /* State for other subsystems/APIs: */ 35 Notifier machine_done; 36 37 /* Pointers to devices and objects: */ 38 HotplugHandler *acpi_dev; 39 ISADevice *rtc; 40 PCIBus *bus; 41 FWCfgState *fw_cfg; 42 qemu_irq *gsi; 43 PFlashCFI01 *flash[2]; 44 45 /* Configuration options: */ 46 uint64_t max_ram_below_4g; 47 OnOffAuto vmport; 48 OnOffAuto smm; 49 50 bool acpi_build_enabled; 51 bool smbus_enabled; 52 bool sata_enabled; 53 bool pit_enabled; 54 55 /* RAM information (sizes, addresses, configuration): */ 56 ram_addr_t below_4g_mem_size, above_4g_mem_size; 57 58 /* CPU and apic information: */ 59 bool apic_xrupt_override; 60 unsigned apic_id_limit; 61 uint16_t boot_cpus; 62 unsigned smp_dies; 63 64 /* NUMA information: */ 65 uint64_t numa_nodes; 66 uint64_t *node_mem; 67 68 /* Address space used by IOAPIC device. All IOAPIC interrupts 69 * will be translated to MSI messages in the address space. */ 70 AddressSpace *ioapic_as; 71 }; 72 73 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 74 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" 75 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 76 #define PC_MACHINE_VMPORT "vmport" 77 #define PC_MACHINE_SMM "smm" 78 #define PC_MACHINE_SMBUS "smbus" 79 #define PC_MACHINE_SATA "sata" 80 #define PC_MACHINE_PIT "pit" 81 82 /** 83 * PCMachineClass: 84 * 85 * Compat fields: 86 * 87 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 88 * backend's alignment value if provided 89 * @acpi_data_size: Size of the chunk of memory at the top of RAM 90 * for the BIOS ACPI tables and other BIOS 91 * datastructures. 92 * @gigabyte_align: Make sure that guest addresses aligned at 93 * 1Gbyte boundaries get mapped to host 94 * addresses aligned at 1Gbyte boundaries. This 95 * way we can use 1GByte pages in the host. 96 * 97 */ 98 typedef struct PCMachineClass { 99 /*< private >*/ 100 MachineClass parent_class; 101 102 /*< public >*/ 103 104 /* Device configuration: */ 105 bool pci_enabled; 106 bool kvmclock_enabled; 107 const char *default_nic_model; 108 109 /* Compat options: */ 110 111 /* Default CPU model version. See x86_cpu_set_default_version(). */ 112 int default_cpu_version; 113 114 /* ACPI compat: */ 115 bool has_acpi_build; 116 bool rsdp_in_ram; 117 int legacy_acpi_table_size; 118 unsigned acpi_data_size; 119 120 /* SMBIOS compat: */ 121 bool smbios_defaults; 122 bool smbios_legacy_mode; 123 bool smbios_uuid_encoded; 124 125 /* RAM / address space compat: */ 126 bool gigabyte_align; 127 bool has_reserved_memory; 128 bool enforce_aligned_dimm; 129 bool broken_reserved_end; 130 131 /* TSC rate migration: */ 132 bool save_tsc_khz; 133 /* generate legacy CPU hotplug AML */ 134 bool legacy_cpu_hotplug; 135 136 /* use DMA capable linuxboot option rom */ 137 bool linuxboot_dma_enabled; 138 139 /* use PVH to load kernels that support this feature */ 140 bool pvh_enabled; 141 142 /* Enables contiguous-apic-ID mode */ 143 bool compat_apic_id_mode; 144 } PCMachineClass; 145 146 #define TYPE_PC_MACHINE "generic-pc-machine" 147 #define PC_MACHINE(obj) \ 148 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE) 149 #define PC_MACHINE_GET_CLASS(obj) \ 150 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE) 151 #define PC_MACHINE_CLASS(klass) \ 152 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) 153 154 /* i8259.c */ 155 156 extern DeviceState *isa_pic; 157 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); 158 qemu_irq *kvm_i8259_init(ISABus *bus); 159 int pic_read_irq(DeviceState *d); 160 int pic_get_output(DeviceState *d); 161 162 /* ioapic.c */ 163 164 /* Global System Interrupts */ 165 166 #define GSI_NUM_PINS IOAPIC_NUM_PINS 167 168 typedef struct GSIState { 169 qemu_irq i8259_irq[ISA_NUM_IRQS]; 170 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 171 } GSIState; 172 173 void gsi_handler(void *opaque, int n, int level); 174 175 /* vmport.c */ 176 #define TYPE_VMPORT "vmport" 177 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); 178 179 static inline void vmport_init(ISABus *bus) 180 { 181 isa_create_simple(bus, TYPE_VMPORT); 182 } 183 184 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); 185 void vmmouse_get_data(uint32_t *data); 186 void vmmouse_set_data(const uint32_t *data); 187 188 /* pc.c */ 189 extern int fd_bootchk; 190 191 bool pc_machine_is_smm_enabled(PCMachineState *pcms); 192 void pc_register_ferr_irq(qemu_irq irq); 193 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 194 195 void pc_cpus_init(PCMachineState *pcms); 196 void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp); 197 void pc_smp_parse(MachineState *ms, QemuOpts *opts); 198 199 void pc_guest_info_init(PCMachineState *pcms); 200 201 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 202 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 203 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 204 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 205 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 206 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 207 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 208 209 210 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 211 MemoryRegion *pci_address_space); 212 213 void xen_load_linux(PCMachineState *pcms); 214 void pc_memory_init(PCMachineState *pcms, 215 MemoryRegion *system_memory, 216 MemoryRegion *rom_memory, 217 MemoryRegion **ram_memory); 218 uint64_t pc_pci_hole64_start(void); 219 qemu_irq pc_allocate_cpu_irq(void); 220 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 221 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 222 ISADevice **rtc_state, 223 bool create_fdctrl, 224 bool no_vmport, 225 bool has_pit, 226 uint32_t hpet_irqs); 227 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 228 void pc_cmos_init(PCMachineState *pcms, 229 BusState *ide0, BusState *ide1, 230 ISADevice *s); 231 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 232 void pc_pci_device_init(PCIBus *pci_bus); 233 234 typedef void (*cpu_set_smm_t)(int smm, void *arg); 235 236 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 237 238 ISADevice *pc_find_fdc0(void); 239 int cmos_get_fd_drive_type(FloppyDriveType fd0); 240 241 #define FW_CFG_IO_BASE 0x510 242 243 #define PORT92_A20_LINE "a20" 244 245 /* acpi_piix.c */ 246 247 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 248 qemu_irq sci_irq, qemu_irq smi_irq, 249 int smm_enabled, DeviceState **piix4_pm); 250 251 /* hpet.c */ 252 extern int no_hpet; 253 254 /* piix_pci.c */ 255 struct PCII440FXState; 256 typedef struct PCII440FXState PCII440FXState; 257 258 #define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost" 259 #define TYPE_I440FX_PCI_DEVICE "i440FX" 260 261 #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX" 262 263 /* 264 * Reset Control Register: PCI-accessible ISA-Compatible Register at address 265 * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000). 266 */ 267 #define RCR_IOPORT 0xcf9 268 269 PCIBus *i440fx_init(const char *host_type, const char *pci_type, 270 PCII440FXState **pi440fx_state, int *piix_devfn, 271 ISABus **isa_bus, qemu_irq *pic, 272 MemoryRegion *address_space_mem, 273 MemoryRegion *address_space_io, 274 ram_addr_t ram_size, 275 ram_addr_t below_4g_mem_size, 276 ram_addr_t above_4g_mem_size, 277 MemoryRegion *pci_memory, 278 MemoryRegion *ram_memory); 279 280 PCIBus *find_i440fx(void); 281 /* piix4.c */ 282 extern PCIDevice *piix4_dev; 283 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); 284 285 /* pc_sysfw.c */ 286 void pc_system_flash_create(PCMachineState *pcms); 287 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 288 289 /* acpi-build.c */ 290 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 291 const CPUArchIdList *apic_ids, GArray *entry); 292 293 /* e820 types */ 294 #define E820_RAM 1 295 #define E820_RESERVED 2 296 #define E820_ACPI 3 297 #define E820_NVS 4 298 #define E820_UNUSABLE 5 299 300 int e820_add_entry(uint64_t, uint64_t, uint32_t); 301 int e820_get_num_entries(void); 302 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); 303 304 extern GlobalProperty pc_compat_4_0[]; 305 extern const size_t pc_compat_4_0_len; 306 307 extern GlobalProperty pc_compat_3_1[]; 308 extern const size_t pc_compat_3_1_len; 309 310 extern GlobalProperty pc_compat_3_0[]; 311 extern const size_t pc_compat_3_0_len; 312 313 extern GlobalProperty pc_compat_2_12[]; 314 extern const size_t pc_compat_2_12_len; 315 316 extern GlobalProperty pc_compat_2_11[]; 317 extern const size_t pc_compat_2_11_len; 318 319 extern GlobalProperty pc_compat_2_10[]; 320 extern const size_t pc_compat_2_10_len; 321 322 extern GlobalProperty pc_compat_2_9[]; 323 extern const size_t pc_compat_2_9_len; 324 325 extern GlobalProperty pc_compat_2_8[]; 326 extern const size_t pc_compat_2_8_len; 327 328 extern GlobalProperty pc_compat_2_7[]; 329 extern const size_t pc_compat_2_7_len; 330 331 extern GlobalProperty pc_compat_2_6[]; 332 extern const size_t pc_compat_2_6_len; 333 334 extern GlobalProperty pc_compat_2_5[]; 335 extern const size_t pc_compat_2_5_len; 336 337 extern GlobalProperty pc_compat_2_4[]; 338 extern const size_t pc_compat_2_4_len; 339 340 extern GlobalProperty pc_compat_2_3[]; 341 extern const size_t pc_compat_2_3_len; 342 343 extern GlobalProperty pc_compat_2_2[]; 344 extern const size_t pc_compat_2_2_len; 345 346 extern GlobalProperty pc_compat_2_1[]; 347 extern const size_t pc_compat_2_1_len; 348 349 extern GlobalProperty pc_compat_2_0[]; 350 extern const size_t pc_compat_2_0_len; 351 352 extern GlobalProperty pc_compat_1_7[]; 353 extern const size_t pc_compat_1_7_len; 354 355 extern GlobalProperty pc_compat_1_6[]; 356 extern const size_t pc_compat_1_6_len; 357 358 extern GlobalProperty pc_compat_1_5[]; 359 extern const size_t pc_compat_1_5_len; 360 361 extern GlobalProperty pc_compat_1_4[]; 362 extern const size_t pc_compat_1_4_len; 363 364 /* Helper for setting model-id for CPU models that changed model-id 365 * depending on QEMU versions up to QEMU 2.4. 366 */ 367 #define PC_CPU_MODEL_IDS(v) \ 368 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 369 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 370 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 371 372 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 373 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 374 { \ 375 MachineClass *mc = MACHINE_CLASS(oc); \ 376 optsfn(mc); \ 377 mc->init = initfn; \ 378 } \ 379 static const TypeInfo pc_machine_type_##suffix = { \ 380 .name = namestr TYPE_MACHINE_SUFFIX, \ 381 .parent = TYPE_PC_MACHINE, \ 382 .class_init = pc_machine_##suffix##_class_init, \ 383 }; \ 384 static void pc_machine_init_##suffix(void) \ 385 { \ 386 type_register(&pc_machine_type_##suffix); \ 387 } \ 388 type_init(pc_machine_init_##suffix) 389 390 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); 391 #endif 392