1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu-common.h" 5 #include "exec/memory.h" 6 #include "hw/boards.h" 7 #include "hw/isa/isa.h" 8 #include "hw/block/fdc.h" 9 #include "net/net.h" 10 #include "hw/i386/ioapic.h" 11 12 #include "qemu/range.h" 13 #include "qemu/bitmap.h" 14 #include "sysemu/sysemu.h" 15 #include "hw/pci/pci.h" 16 #include "hw/boards.h" 17 18 #define HPET_INTCAP "hpet-intcap" 19 20 /** 21 * PCMachineState: 22 * @hotplug_memory_base: address in guest RAM address space where hotplug memory 23 * address space begins. 24 * @hotplug_memory: hotplug memory addess space container 25 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 26 */ 27 struct PCMachineState { 28 /*< private >*/ 29 MachineState parent_obj; 30 31 /* <public> */ 32 ram_addr_t hotplug_memory_base; 33 MemoryRegion hotplug_memory; 34 35 HotplugHandler *acpi_dev; 36 37 uint64_t max_ram_below_4g; 38 }; 39 40 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 41 #define PC_MACHINE_MEMHP_REGION_SIZE "hotplug-memory-region-size" 42 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 43 44 /** 45 * PCMachineClass: 46 * @get_hotplug_handler: pointer to parent class callback @get_hotplug_handler 47 */ 48 struct PCMachineClass { 49 /*< private >*/ 50 MachineClass parent_class; 51 52 /*< public >*/ 53 HotplugHandler *(*get_hotplug_handler)(MachineState *machine, 54 DeviceState *dev); 55 }; 56 57 typedef struct PCMachineState PCMachineState; 58 typedef struct PCMachineClass PCMachineClass; 59 60 #define TYPE_PC_MACHINE "generic-pc-machine" 61 #define PC_MACHINE(obj) \ 62 OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE) 63 #define PC_MACHINE_GET_CLASS(obj) \ 64 OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE) 65 #define PC_MACHINE_CLASS(klass) \ 66 OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE) 67 68 void qemu_register_pc_machine(QEMUMachine *m); 69 70 /* PC-style peripherals (also used by other machines). */ 71 72 typedef struct PcPciInfo { 73 Range w32; 74 Range w64; 75 } PcPciInfo; 76 77 #define ACPI_PM_PROP_S3_DISABLED "disable_s3" 78 #define ACPI_PM_PROP_S4_DISABLED "disable_s4" 79 #define ACPI_PM_PROP_S4_VAL "s4_val" 80 #define ACPI_PM_PROP_SCI_INT "sci_int" 81 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd" 82 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd" 83 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base" 84 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk" 85 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len" 86 87 struct PcGuestInfo { 88 bool has_pci_info; 89 bool isapc_ram_fw; 90 hwaddr ram_size, ram_size_below_4g; 91 unsigned apic_id_limit; 92 bool apic_xrupt_override; 93 uint64_t numa_nodes; 94 uint64_t *node_mem; 95 uint64_t *node_cpu; 96 FWCfgState *fw_cfg; 97 bool has_acpi_build; 98 bool has_reserved_memory; 99 }; 100 101 /* parallel.c */ 102 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr) 103 { 104 DeviceState *dev; 105 ISADevice *isadev; 106 107 isadev = isa_try_create(bus, "isa-parallel"); 108 if (!isadev) { 109 return false; 110 } 111 dev = DEVICE(isadev); 112 qdev_prop_set_uint32(dev, "index", index); 113 qdev_prop_set_chr(dev, "chardev", chr); 114 if (qdev_init(dev) < 0) { 115 return false; 116 } 117 return true; 118 } 119 120 bool parallel_mm_init(MemoryRegion *address_space, 121 hwaddr base, int it_shift, qemu_irq irq, 122 CharDriverState *chr); 123 124 /* i8259.c */ 125 126 extern DeviceState *isa_pic; 127 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq); 128 qemu_irq *kvm_i8259_init(ISABus *bus); 129 int pic_read_irq(DeviceState *d); 130 int pic_get_output(DeviceState *d); 131 void pic_info(Monitor *mon, const QDict *qdict); 132 void irq_info(Monitor *mon, const QDict *qdict); 133 134 /* Global System Interrupts */ 135 136 #define GSI_NUM_PINS IOAPIC_NUM_PINS 137 138 typedef struct GSIState { 139 qemu_irq i8259_irq[ISA_NUM_IRQS]; 140 qemu_irq ioapic_irq[IOAPIC_NUM_PINS]; 141 } GSIState; 142 143 void gsi_handler(void *opaque, int n, int level); 144 145 /* vmport.c */ 146 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address); 147 148 static inline void vmport_init(ISABus *bus) 149 { 150 isa_create_simple(bus, "vmport"); 151 } 152 153 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque); 154 void vmmouse_get_data(uint32_t *data); 155 void vmmouse_set_data(const uint32_t *data); 156 157 /* pckbd.c */ 158 159 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base); 160 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq, 161 MemoryRegion *region, ram_addr_t size, 162 hwaddr mask); 163 void i8042_isa_mouse_fake_event(void *opaque); 164 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out); 165 166 /* pc.c */ 167 extern int fd_bootchk; 168 169 void pc_register_ferr_irq(qemu_irq irq); 170 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 171 172 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge); 173 void pc_hot_add_cpu(const int64_t id, Error **errp); 174 void pc_acpi_init(const char *default_dsdt); 175 176 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size, 177 ram_addr_t above_4g_mem_size); 178 179 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 180 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 181 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 182 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 183 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 184 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL) 185 186 187 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 188 MemoryRegion *pci_address_space); 189 190 FWCfgState *pc_memory_init(MachineState *machine, 191 MemoryRegion *system_memory, 192 ram_addr_t below_4g_mem_size, 193 ram_addr_t above_4g_mem_size, 194 MemoryRegion *rom_memory, 195 MemoryRegion **ram_memory, 196 PcGuestInfo *guest_info); 197 qemu_irq *pc_allocate_cpu_irq(void); 198 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 199 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, 200 ISADevice **rtc_state, 201 ISADevice **floppy, 202 bool no_vmport, 203 uint32 hpet_irqs); 204 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 205 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size, 206 const char *boot_device, 207 ISADevice *floppy, BusState *ide0, BusState *ide1, 208 ISADevice *s); 209 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus); 210 void pc_pci_device_init(PCIBus *pci_bus); 211 212 typedef void (*cpu_set_smm_t)(int smm, void *arg); 213 void cpu_smm_register(cpu_set_smm_t callback, void *arg); 214 215 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name); 216 217 /* acpi_piix.c */ 218 219 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, 220 qemu_irq sci_irq, qemu_irq smi_irq, 221 int kvm_enabled, FWCfgState *fw_cfg, 222 DeviceState **piix4_pm); 223 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); 224 225 /* hpet.c */ 226 extern int no_hpet; 227 228 /* piix_pci.c */ 229 struct PCII440FXState; 230 typedef struct PCII440FXState PCII440FXState; 231 232 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn, 233 ISABus **isa_bus, qemu_irq *pic, 234 MemoryRegion *address_space_mem, 235 MemoryRegion *address_space_io, 236 ram_addr_t ram_size, 237 ram_addr_t below_4g_mem_size, 238 ram_addr_t above_4g_mem_size, 239 MemoryRegion *pci_memory, 240 MemoryRegion *ram_memory); 241 242 PCIBus *find_i440fx(void); 243 /* piix4.c */ 244 extern PCIDevice *piix4_dev; 245 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn); 246 247 /* vga.c */ 248 enum vga_retrace_method { 249 VGA_RETRACE_DUMB, 250 VGA_RETRACE_PRECISE 251 }; 252 253 extern enum vga_retrace_method vga_retrace_method; 254 255 int isa_vga_mm_init(hwaddr vram_base, 256 hwaddr ctrl_base, int it_shift, 257 MemoryRegion *address_space); 258 259 /* ne2000.c */ 260 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd) 261 { 262 DeviceState *dev; 263 ISADevice *isadev; 264 265 qemu_check_nic_model(nd, "ne2k_isa"); 266 267 isadev = isa_try_create(bus, "ne2k_isa"); 268 if (!isadev) { 269 return false; 270 } 271 dev = DEVICE(isadev); 272 qdev_prop_set_uint32(dev, "iobase", base); 273 qdev_prop_set_uint32(dev, "irq", irq); 274 qdev_set_nic_properties(dev, nd); 275 qdev_init_nofail(dev); 276 return true; 277 } 278 279 /* pc_sysfw.c */ 280 void pc_system_firmware_init(MemoryRegion *rom_memory, 281 bool isapc_ram_fw); 282 283 /* pvpanic.c */ 284 uint16_t pvpanic_port(void); 285 286 /* e820 types */ 287 #define E820_RAM 1 288 #define E820_RESERVED 2 289 #define E820_ACPI 3 290 #define E820_NVS 4 291 #define E820_UNUSABLE 5 292 293 int e820_add_entry(uint64_t, uint64_t, uint32_t); 294 int e820_get_num_entries(void); 295 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); 296 297 #define PC_Q35_COMPAT_2_0 \ 298 PC_COMPAT_2_0, \ 299 {\ 300 .driver = "ICH9-LPC",\ 301 .property = "memory-hotplug-support",\ 302 .value = "off",\ 303 },{\ 304 .driver = "xio3130-downstream",\ 305 .property = COMPAT_PROP_PCP,\ 306 .value = "off",\ 307 },{\ 308 .driver = "ioh3420",\ 309 .property = COMPAT_PROP_PCP,\ 310 .value = "off",\ 311 } 312 313 #define PC_Q35_COMPAT_1_7 \ 314 PC_COMPAT_1_7, \ 315 PC_Q35_COMPAT_2_0, \ 316 {\ 317 .driver = "hpet",\ 318 .property = HPET_INTCAP,\ 319 .value = stringify(4),\ 320 } 321 322 #define PC_Q35_COMPAT_1_6 \ 323 PC_COMPAT_1_6, \ 324 PC_Q35_COMPAT_1_7 325 326 #define PC_Q35_COMPAT_1_5 \ 327 PC_COMPAT_1_5, \ 328 PC_Q35_COMPAT_1_6 329 330 #define PC_Q35_COMPAT_1_4 \ 331 PC_COMPAT_1_4, \ 332 PC_Q35_COMPAT_1_5 333 334 #define PC_COMPAT_2_0 \ 335 {\ 336 .driver = "virtio-scsi-pci",\ 337 .property = "any_layout",\ 338 .value = "off",\ 339 },{\ 340 .driver = "PIIX4_PM",\ 341 .property = "memory-hotplug-support",\ 342 .value = "off",\ 343 },\ 344 {\ 345 .driver = "apic",\ 346 .property = "version",\ 347 .value = stringify(0x11),\ 348 },\ 349 {\ 350 .driver = "nec-usb-xhci",\ 351 .property = "superspeed-ports-first",\ 352 .value = "off",\ 353 },\ 354 {\ 355 .driver = "pci-serial",\ 356 .property = "prog_if",\ 357 .value = stringify(0),\ 358 },\ 359 {\ 360 .driver = "pci-serial-2x",\ 361 .property = "prof_if",\ 362 .value = stringify(0),\ 363 },\ 364 {\ 365 .driver = "pci-serial-4x",\ 366 .property = "prog_if",\ 367 .value = stringify(0),\ 368 },\ 369 {\ 370 .driver = "virtio-net-pci",\ 371 .property = "guest_announce",\ 372 .value = "off",\ 373 } 374 375 #define PC_COMPAT_1_7 \ 376 PC_COMPAT_2_0, \ 377 {\ 378 .driver = TYPE_USB_DEVICE,\ 379 .property = "msos-desc",\ 380 .value = "no",\ 381 },\ 382 {\ 383 .driver = "PIIX4_PM",\ 384 .property = "acpi-pci-hotplug-with-bridge-support",\ 385 .value = "off",\ 386 } 387 388 #define PC_COMPAT_1_6 \ 389 PC_COMPAT_1_7, \ 390 {\ 391 .driver = "e1000",\ 392 .property = "mitigation",\ 393 .value = "off",\ 394 },{\ 395 .driver = "qemu64-" TYPE_X86_CPU,\ 396 .property = "model",\ 397 .value = stringify(2),\ 398 },{\ 399 .driver = "qemu32-" TYPE_X86_CPU,\ 400 .property = "model",\ 401 .value = stringify(3),\ 402 },{\ 403 .driver = "i440FX-pcihost",\ 404 .property = "short_root_bus",\ 405 .value = stringify(1),\ 406 },{\ 407 .driver = "q35-pcihost",\ 408 .property = "short_root_bus",\ 409 .value = stringify(1),\ 410 } 411 412 #define PC_COMPAT_1_5 \ 413 PC_COMPAT_1_6, \ 414 {\ 415 .driver = "Conroe-" TYPE_X86_CPU,\ 416 .property = "model",\ 417 .value = stringify(2),\ 418 },{\ 419 .driver = "Conroe-" TYPE_X86_CPU,\ 420 .property = "level",\ 421 .value = stringify(2),\ 422 },{\ 423 .driver = "Penryn-" TYPE_X86_CPU,\ 424 .property = "model",\ 425 .value = stringify(2),\ 426 },{\ 427 .driver = "Penryn-" TYPE_X86_CPU,\ 428 .property = "level",\ 429 .value = stringify(2),\ 430 },{\ 431 .driver = "Nehalem-" TYPE_X86_CPU,\ 432 .property = "model",\ 433 .value = stringify(2),\ 434 },{\ 435 .driver = "Nehalem-" TYPE_X86_CPU,\ 436 .property = "level",\ 437 .value = stringify(2),\ 438 },{\ 439 .driver = "virtio-net-pci",\ 440 .property = "any_layout",\ 441 .value = "off",\ 442 },{\ 443 .driver = TYPE_X86_CPU,\ 444 .property = "pmu",\ 445 .value = "on",\ 446 },{\ 447 .driver = "i440FX-pcihost",\ 448 .property = "short_root_bus",\ 449 .value = stringify(0),\ 450 },{\ 451 .driver = "q35-pcihost",\ 452 .property = "short_root_bus",\ 453 .value = stringify(0),\ 454 } 455 456 #define PC_COMPAT_1_4 \ 457 PC_COMPAT_1_5, \ 458 {\ 459 .driver = "scsi-hd",\ 460 .property = "discard_granularity",\ 461 .value = stringify(0),\ 462 },{\ 463 .driver = "scsi-cd",\ 464 .property = "discard_granularity",\ 465 .value = stringify(0),\ 466 },{\ 467 .driver = "scsi-disk",\ 468 .property = "discard_granularity",\ 469 .value = stringify(0),\ 470 },{\ 471 .driver = "ide-hd",\ 472 .property = "discard_granularity",\ 473 .value = stringify(0),\ 474 },{\ 475 .driver = "ide-cd",\ 476 .property = "discard_granularity",\ 477 .value = stringify(0),\ 478 },{\ 479 .driver = "ide-drive",\ 480 .property = "discard_granularity",\ 481 .value = stringify(0),\ 482 },{\ 483 .driver = "virtio-blk-pci",\ 484 .property = "discard_granularity",\ 485 .value = stringify(0),\ 486 },{\ 487 .driver = "virtio-serial-pci",\ 488 .property = "vectors",\ 489 /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\ 490 .value = stringify(0xFFFFFFFF),\ 491 },{ \ 492 .driver = "virtio-net-pci", \ 493 .property = "ctrl_guest_offloads", \ 494 .value = "off", \ 495 },{\ 496 .driver = "e1000",\ 497 .property = "romfile",\ 498 .value = "pxe-e1000.rom",\ 499 },{\ 500 .driver = "ne2k_pci",\ 501 .property = "romfile",\ 502 .value = "pxe-ne2k_pci.rom",\ 503 },{\ 504 .driver = "pcnet",\ 505 .property = "romfile",\ 506 .value = "pxe-pcnet.rom",\ 507 },{\ 508 .driver = "rtl8139",\ 509 .property = "romfile",\ 510 .value = "pxe-rtl8139.rom",\ 511 },{\ 512 .driver = "virtio-net-pci",\ 513 .property = "romfile",\ 514 .value = "pxe-virtio.rom",\ 515 },{\ 516 .driver = "486-" TYPE_X86_CPU,\ 517 .property = "model",\ 518 .value = stringify(0),\ 519 } 520 521 #define PC_COMMON_MACHINE_OPTIONS \ 522 .default_boot_order = "cad" 523 524 #define PC_DEFAULT_MACHINE_OPTIONS \ 525 PC_COMMON_MACHINE_OPTIONS, \ 526 .hot_add_cpu = pc_hot_add_cpu, \ 527 .max_cpus = 255 528 529 #endif 530