1 #ifndef HW_PC_H 2 #define HW_PC_H 3 4 #include "qemu/notify.h" 5 #include "qapi/qapi-types-common.h" 6 #include "qemu/uuid.h" 7 #include "hw/boards.h" 8 #include "hw/block/fdc.h" 9 #include "hw/block/flash.h" 10 #include "hw/i386/x86.h" 11 12 #include "hw/acpi/acpi_dev_interface.h" 13 #include "hw/hotplug.h" 14 #include "qom/object.h" 15 #include "hw/i386/sgx-epc.h" 16 #include "hw/firmware/smbios.h" 17 18 #define HPET_INTCAP "hpet-intcap" 19 20 /** 21 * PCMachineState: 22 * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling 23 * @boot_cpus: number of present VCPUs 24 */ 25 typedef struct PCMachineState { 26 /*< private >*/ 27 X86MachineState parent_obj; 28 29 /* <public> */ 30 31 /* State for other subsystems/APIs: */ 32 Notifier machine_done; 33 34 /* Pointers to devices and objects: */ 35 PCIBus *bus; 36 I2CBus *smbus; 37 PFlashCFI01 *flash[2]; 38 ISADevice *pcspk; 39 DeviceState *iommu; 40 41 /* Configuration options: */ 42 uint64_t max_ram_below_4g; 43 OnOffAuto vmport; 44 SmbiosEntryPointType smbios_entry_point_type; 45 46 bool acpi_build_enabled; 47 bool smbus_enabled; 48 bool sata_enabled; 49 bool pit_enabled; 50 bool hpet_enabled; 51 bool i8042_enabled; 52 bool default_bus_bypass_iommu; 53 uint64_t max_fw_size; 54 55 /* ACPI Memory hotplug IO base address */ 56 hwaddr memhp_io_base; 57 58 SGXEPCState sgx_epc; 59 } PCMachineState; 60 61 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device" 62 #define PC_MACHINE_MAX_RAM_BELOW_4G "max-ram-below-4g" 63 #define PC_MACHINE_DEVMEM_REGION_SIZE "device-memory-region-size" 64 #define PC_MACHINE_VMPORT "vmport" 65 #define PC_MACHINE_SMBUS "smbus" 66 #define PC_MACHINE_SATA "sata" 67 #define PC_MACHINE_PIT "pit" 68 #define PC_MACHINE_I8042 "i8042" 69 #define PC_MACHINE_MAX_FW_SIZE "max-fw-size" 70 #define PC_MACHINE_SMBIOS_EP "smbios-entry-point-type" 71 72 /** 73 * PCMachineClass: 74 * 75 * Compat fields: 76 * 77 * @enforce_aligned_dimm: check that DIMM's address/size is aligned by 78 * backend's alignment value if provided 79 * @acpi_data_size: Size of the chunk of memory at the top of RAM 80 * for the BIOS ACPI tables and other BIOS 81 * datastructures. 82 * @gigabyte_align: Make sure that guest addresses aligned at 83 * 1Gbyte boundaries get mapped to host 84 * addresses aligned at 1Gbyte boundaries. This 85 * way we can use 1GByte pages in the host. 86 * 87 */ 88 struct PCMachineClass { 89 /*< private >*/ 90 X86MachineClass parent_class; 91 92 /*< public >*/ 93 94 /* Device configuration: */ 95 bool pci_enabled; 96 bool kvmclock_enabled; 97 const char *default_nic_model; 98 99 /* Compat options: */ 100 101 /* Default CPU model version. See x86_cpu_set_default_version(). */ 102 int default_cpu_version; 103 104 /* ACPI compat: */ 105 bool has_acpi_build; 106 bool rsdp_in_ram; 107 int legacy_acpi_table_size; 108 unsigned acpi_data_size; 109 bool do_not_add_smb_acpi; 110 int pci_root_uid; 111 112 /* SMBIOS compat: */ 113 bool smbios_defaults; 114 bool smbios_legacy_mode; 115 bool smbios_uuid_encoded; 116 117 /* RAM / address space compat: */ 118 bool gigabyte_align; 119 bool has_reserved_memory; 120 bool enforce_aligned_dimm; 121 bool broken_reserved_end; 122 123 /* generate legacy CPU hotplug AML */ 124 bool legacy_cpu_hotplug; 125 126 /* use PVH to load kernels that support this feature */ 127 bool pvh_enabled; 128 129 /* create kvmclock device even when KVM PV features are not exposed */ 130 bool kvmclock_create_always; 131 }; 132 133 #define TYPE_PC_MACHINE "generic-pc-machine" 134 OBJECT_DECLARE_TYPE(PCMachineState, PCMachineClass, PC_MACHINE) 135 136 /* ioapic.c */ 137 138 GSIState *pc_gsi_create(qemu_irq **irqs, bool pci_enabled); 139 140 /* pc.c */ 141 extern int fd_bootchk; 142 143 void pc_acpi_smi_interrupt(void *opaque, int irq, int level); 144 145 void pc_guest_info_init(PCMachineState *pcms); 146 147 #define PCI_HOST_PROP_PCI_HOLE_START "pci-hole-start" 148 #define PCI_HOST_PROP_PCI_HOLE_END "pci-hole-end" 149 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start" 150 #define PCI_HOST_PROP_PCI_HOLE64_END "pci-hole64-end" 151 #define PCI_HOST_PROP_PCI_HOLE64_SIZE "pci-hole64-size" 152 #define PCI_HOST_BELOW_4G_MEM_SIZE "below-4g-mem-size" 153 #define PCI_HOST_ABOVE_4G_MEM_SIZE "above-4g-mem-size" 154 155 156 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory, 157 MemoryRegion *pci_address_space); 158 159 void xen_load_linux(PCMachineState *pcms); 160 void pc_memory_init(PCMachineState *pcms, 161 MemoryRegion *system_memory, 162 MemoryRegion *rom_memory, 163 MemoryRegion **ram_memory); 164 uint64_t pc_pci_hole64_start(void); 165 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus); 166 void pc_basic_device_init(struct PCMachineState *pcms, 167 ISABus *isa_bus, qemu_irq *gsi, 168 ISADevice **rtc_state, 169 bool create_fdctrl, 170 uint32_t hpet_irqs); 171 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd); 172 void pc_cmos_init(PCMachineState *pcms, 173 BusState *ide0, BusState *ide1, 174 ISADevice *s); 175 void pc_nic_init(PCMachineClass *pcmc, ISABus *isa_bus, PCIBus *pci_bus); 176 void pc_pci_device_init(PCIBus *pci_bus); 177 178 typedef void (*cpu_set_smm_t)(int smm, void *arg); 179 180 void pc_i8259_create(ISABus *isa_bus, qemu_irq *i8259_irqs); 181 182 ISADevice *pc_find_fdc0(void); 183 184 /* port92.c */ 185 #define PORT92_A20_LINE "a20" 186 187 #define TYPE_PORT92 "port92" 188 189 /* pc_sysfw.c */ 190 void pc_system_flash_create(PCMachineState *pcms); 191 void pc_system_flash_cleanup_unused(PCMachineState *pcms); 192 void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); 193 bool pc_system_ovmf_table_find(const char *entry, uint8_t **data, 194 int *data_len); 195 void pc_system_parse_ovmf_flash(uint8_t *flash_ptr, size_t flash_size); 196 197 /* hw/i386/acpi-common.c */ 198 void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, 199 const CPUArchIdList *apic_ids, GArray *entry, 200 bool force_enabled); 201 202 /* sgx.c */ 203 void pc_machine_init_sgx_epc(PCMachineState *pcms); 204 205 extern GlobalProperty pc_compat_7_0[]; 206 extern const size_t pc_compat_7_0_len; 207 208 extern GlobalProperty pc_compat_6_2[]; 209 extern const size_t pc_compat_6_2_len; 210 211 extern GlobalProperty pc_compat_6_1[]; 212 extern const size_t pc_compat_6_1_len; 213 214 extern GlobalProperty pc_compat_6_0[]; 215 extern const size_t pc_compat_6_0_len; 216 217 extern GlobalProperty pc_compat_5_2[]; 218 extern const size_t pc_compat_5_2_len; 219 220 extern GlobalProperty pc_compat_5_1[]; 221 extern const size_t pc_compat_5_1_len; 222 223 extern GlobalProperty pc_compat_5_0[]; 224 extern const size_t pc_compat_5_0_len; 225 226 extern GlobalProperty pc_compat_4_2[]; 227 extern const size_t pc_compat_4_2_len; 228 229 extern GlobalProperty pc_compat_4_1[]; 230 extern const size_t pc_compat_4_1_len; 231 232 extern GlobalProperty pc_compat_4_0[]; 233 extern const size_t pc_compat_4_0_len; 234 235 extern GlobalProperty pc_compat_3_1[]; 236 extern const size_t pc_compat_3_1_len; 237 238 extern GlobalProperty pc_compat_3_0[]; 239 extern const size_t pc_compat_3_0_len; 240 241 extern GlobalProperty pc_compat_2_12[]; 242 extern const size_t pc_compat_2_12_len; 243 244 extern GlobalProperty pc_compat_2_11[]; 245 extern const size_t pc_compat_2_11_len; 246 247 extern GlobalProperty pc_compat_2_10[]; 248 extern const size_t pc_compat_2_10_len; 249 250 extern GlobalProperty pc_compat_2_9[]; 251 extern const size_t pc_compat_2_9_len; 252 253 extern GlobalProperty pc_compat_2_8[]; 254 extern const size_t pc_compat_2_8_len; 255 256 extern GlobalProperty pc_compat_2_7[]; 257 extern const size_t pc_compat_2_7_len; 258 259 extern GlobalProperty pc_compat_2_6[]; 260 extern const size_t pc_compat_2_6_len; 261 262 extern GlobalProperty pc_compat_2_5[]; 263 extern const size_t pc_compat_2_5_len; 264 265 extern GlobalProperty pc_compat_2_4[]; 266 extern const size_t pc_compat_2_4_len; 267 268 extern GlobalProperty pc_compat_2_3[]; 269 extern const size_t pc_compat_2_3_len; 270 271 extern GlobalProperty pc_compat_2_2[]; 272 extern const size_t pc_compat_2_2_len; 273 274 extern GlobalProperty pc_compat_2_1[]; 275 extern const size_t pc_compat_2_1_len; 276 277 extern GlobalProperty pc_compat_2_0[]; 278 extern const size_t pc_compat_2_0_len; 279 280 extern GlobalProperty pc_compat_1_7[]; 281 extern const size_t pc_compat_1_7_len; 282 283 extern GlobalProperty pc_compat_1_6[]; 284 extern const size_t pc_compat_1_6_len; 285 286 extern GlobalProperty pc_compat_1_5[]; 287 extern const size_t pc_compat_1_5_len; 288 289 extern GlobalProperty pc_compat_1_4[]; 290 extern const size_t pc_compat_1_4_len; 291 292 /* Helper for setting model-id for CPU models that changed model-id 293 * depending on QEMU versions up to QEMU 2.4. 294 */ 295 #define PC_CPU_MODEL_IDS(v) \ 296 { "qemu32-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 297 { "qemu64-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, },\ 298 { "athlon-" TYPE_X86_CPU, "model-id", "QEMU Virtual CPU version " v, }, 299 300 #define DEFINE_PC_MACHINE(suffix, namestr, initfn, optsfn) \ 301 static void pc_machine_##suffix##_class_init(ObjectClass *oc, void *data) \ 302 { \ 303 MachineClass *mc = MACHINE_CLASS(oc); \ 304 optsfn(mc); \ 305 mc->init = initfn; \ 306 } \ 307 static const TypeInfo pc_machine_type_##suffix = { \ 308 .name = namestr TYPE_MACHINE_SUFFIX, \ 309 .parent = TYPE_PC_MACHINE, \ 310 .class_init = pc_machine_##suffix##_class_init, \ 311 }; \ 312 static void pc_machine_init_##suffix(void) \ 313 { \ 314 type_register(&pc_machine_type_##suffix); \ 315 } \ 316 type_init(pc_machine_init_##suffix) 317 318 extern void igd_passthrough_isa_bridge_create(PCIBus *bus, uint16_t gpu_dev_id); 319 #endif 320