1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef INTEL_IOMMU_H 23 #define INTEL_IOMMU_H 24 #include "hw/qdev.h" 25 #include "sysemu/dma.h" 26 #include "hw/i386/x86-iommu.h" 27 #include "hw/i386/ioapic.h" 28 #include "hw/pci/msi.h" 29 30 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" 31 #define INTEL_IOMMU_DEVICE(obj) \ 32 OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) 33 34 /* DMAR Hardware Unit Definition address (IOMMU unit) */ 35 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL 36 37 #define VTD_PCI_BUS_MAX 256 38 #define VTD_PCI_SLOT_MAX 32 39 #define VTD_PCI_FUNC_MAX 8 40 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 41 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) 42 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff) 43 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) 44 45 #define DMAR_REG_SIZE 0x230 46 #define VTD_HOST_ADDRESS_WIDTH 39 47 #define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1) 48 49 #define DMAR_REPORT_F_INTR (1) 50 51 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) 52 #define VTD_MSI_ADDR_HI_SHIFT (32) 53 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) 54 55 typedef struct VTDContextEntry VTDContextEntry; 56 typedef struct VTDContextCacheEntry VTDContextCacheEntry; 57 typedef struct IntelIOMMUState IntelIOMMUState; 58 typedef struct VTDAddressSpace VTDAddressSpace; 59 typedef struct VTDIOTLBEntry VTDIOTLBEntry; 60 typedef struct VTDBus VTDBus; 61 typedef union VTD_IRTE VTD_IRTE; 62 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; 63 typedef struct VTDIrq VTDIrq; 64 typedef struct VTD_MSIMessage VTD_MSIMessage; 65 66 /* Context-Entry */ 67 struct VTDContextEntry { 68 uint64_t lo; 69 uint64_t hi; 70 }; 71 72 struct VTDContextCacheEntry { 73 /* The cache entry is obsolete if 74 * context_cache_gen!=IntelIOMMUState.context_cache_gen 75 */ 76 uint32_t context_cache_gen; 77 struct VTDContextEntry context_entry; 78 }; 79 80 struct VTDAddressSpace { 81 PCIBus *bus; 82 uint8_t devfn; 83 AddressSpace as; 84 MemoryRegion iommu; 85 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ 86 IntelIOMMUState *iommu_state; 87 VTDContextCacheEntry context_cache_entry; 88 }; 89 90 struct VTDBus { 91 PCIBus* bus; /* A reference to the bus to provide translation for */ 92 VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */ 93 }; 94 95 struct VTDIOTLBEntry { 96 uint64_t gfn; 97 uint16_t domain_id; 98 uint64_t slpte; 99 uint64_t mask; 100 bool read_flags; 101 bool write_flags; 102 }; 103 104 /* Interrupt Remapping Table Entry Definition */ 105 union VTD_IRTE { 106 struct { 107 #ifdef HOST_WORDS_BIGENDIAN 108 uint32_t dest_id:32; /* Destination ID */ 109 uint32_t __reserved_1:8; /* Reserved 1 */ 110 uint32_t vector:8; /* Interrupt Vector */ 111 uint32_t irte_mode:1; /* IRTE Mode */ 112 uint32_t __reserved_0:3; /* Reserved 0 */ 113 uint32_t __avail:4; /* Available spaces for software */ 114 uint32_t delivery_mode:3; /* Delivery Mode */ 115 uint32_t trigger_mode:1; /* Trigger Mode */ 116 uint32_t redir_hint:1; /* Redirection Hint */ 117 uint32_t dest_mode:1; /* Destination Mode */ 118 uint32_t fault_disable:1; /* Fault Processing Disable */ 119 uint32_t present:1; /* Whether entry present/available */ 120 #else 121 uint32_t present:1; /* Whether entry present/available */ 122 uint32_t fault_disable:1; /* Fault Processing Disable */ 123 uint32_t dest_mode:1; /* Destination Mode */ 124 uint32_t redir_hint:1; /* Redirection Hint */ 125 uint32_t trigger_mode:1; /* Trigger Mode */ 126 uint32_t delivery_mode:3; /* Delivery Mode */ 127 uint32_t __avail:4; /* Available spaces for software */ 128 uint32_t __reserved_0:3; /* Reserved 0 */ 129 uint32_t irte_mode:1; /* IRTE Mode */ 130 uint32_t vector:8; /* Interrupt Vector */ 131 uint32_t __reserved_1:8; /* Reserved 1 */ 132 uint32_t dest_id:32; /* Destination ID */ 133 #endif 134 uint16_t source_id:16; /* Source-ID */ 135 #ifdef HOST_WORDS_BIGENDIAN 136 uint64_t __reserved_2:44; /* Reserved 2 */ 137 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 138 uint64_t sid_q:2; /* Source-ID Qualifier */ 139 #else 140 uint64_t sid_q:2; /* Source-ID Qualifier */ 141 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 142 uint64_t __reserved_2:44; /* Reserved 2 */ 143 #endif 144 } QEMU_PACKED; 145 uint64_t data[2]; 146 }; 147 148 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */ 149 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */ 150 151 /* Programming format for MSI/MSI-X addresses */ 152 union VTD_IR_MSIAddress { 153 struct { 154 #ifdef HOST_WORDS_BIGENDIAN 155 uint32_t __head:12; /* Should always be: 0x0fee */ 156 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 157 uint32_t int_mode:1; /* Interrupt format */ 158 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 159 uint32_t index_h:1; /* Interrupt index bit 15 */ 160 uint32_t __not_care:2; 161 #else 162 uint32_t __not_care:2; 163 uint32_t index_h:1; /* Interrupt index bit 15 */ 164 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 165 uint32_t int_mode:1; /* Interrupt format */ 166 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 167 uint32_t __head:12; /* Should always be: 0x0fee */ 168 #endif 169 } QEMU_PACKED; 170 uint32_t data; 171 }; 172 173 /* Generic IRQ entry information */ 174 struct VTDIrq { 175 /* Used by both IOAPIC/MSI interrupt remapping */ 176 uint8_t trigger_mode; 177 uint8_t vector; 178 uint8_t delivery_mode; 179 uint32_t dest; 180 uint8_t dest_mode; 181 182 /* only used by MSI interrupt remapping */ 183 uint8_t redir_hint; 184 uint8_t msi_addr_last_bits; 185 }; 186 187 struct VTD_MSIMessage { 188 union { 189 struct { 190 #ifdef HOST_WORDS_BIGENDIAN 191 uint32_t __addr_head:12; /* 0xfee */ 192 uint32_t dest:8; 193 uint32_t __reserved:8; 194 uint32_t redir_hint:1; 195 uint32_t dest_mode:1; 196 uint32_t __not_used:2; 197 #else 198 uint32_t __not_used:2; 199 uint32_t dest_mode:1; 200 uint32_t redir_hint:1; 201 uint32_t __reserved:8; 202 uint32_t dest:8; 203 uint32_t __addr_head:12; /* 0xfee */ 204 #endif 205 uint32_t __addr_hi:32; 206 } QEMU_PACKED; 207 uint64_t msi_addr; 208 }; 209 union { 210 struct { 211 #ifdef HOST_WORDS_BIGENDIAN 212 uint16_t trigger_mode:1; 213 uint16_t level:1; 214 uint16_t __resved:3; 215 uint16_t delivery_mode:3; 216 uint16_t vector:8; 217 #else 218 uint16_t vector:8; 219 uint16_t delivery_mode:3; 220 uint16_t __resved:3; 221 uint16_t level:1; 222 uint16_t trigger_mode:1; 223 #endif 224 uint16_t __resved1:16; 225 } QEMU_PACKED; 226 uint32_t msi_data; 227 }; 228 }; 229 230 /* When IR is enabled, all MSI/MSI-X data bits should be zero */ 231 #define VTD_IR_MSI_DATA (0) 232 233 /* The iommu (DMAR) device state struct */ 234 struct IntelIOMMUState { 235 X86IOMMUState x86_iommu; 236 MemoryRegion csrmem; 237 uint8_t csr[DMAR_REG_SIZE]; /* register values */ 238 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ 239 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ 240 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ 241 uint32_t version; 242 243 dma_addr_t root; /* Current root table pointer */ 244 bool root_extended; /* Type of root table (extended or not) */ 245 bool dmar_enabled; /* Set if DMA remapping is enabled */ 246 247 uint16_t iq_head; /* Current invalidation queue head */ 248 uint16_t iq_tail; /* Current invalidation queue tail */ 249 dma_addr_t iq; /* Current invalidation queue pointer */ 250 uint16_t iq_size; /* IQ Size in number of entries */ 251 bool qi_enabled; /* Set if the QI is enabled */ 252 uint8_t iq_last_desc_type; /* The type of last completed descriptor */ 253 254 /* The index of the Fault Recording Register to be used next. 255 * Wraps around from N-1 to 0, where N is the number of FRCD_REG. 256 */ 257 uint16_t next_frcd_reg; 258 259 uint64_t cap; /* The value of capability reg */ 260 uint64_t ecap; /* The value of extended capability reg */ 261 262 uint32_t context_cache_gen; /* Should be in [1,MAX] */ 263 GHashTable *iotlb; /* IOTLB */ 264 265 MemoryRegionIOMMUOps iommu_ops; 266 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */ 267 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */ 268 269 /* interrupt remapping */ 270 bool intr_enabled; /* Whether guest enabled IR */ 271 dma_addr_t intr_root; /* Interrupt remapping table pointer */ 272 uint32_t intr_size; /* Number of IR table entries */ 273 }; 274 275 /* Find the VTD Address space associated with the given bus pointer, 276 * create a new one if none exists 277 */ 278 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn); 279 280 #endif 281