1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef INTEL_IOMMU_H 23 #define INTEL_IOMMU_H 24 #include "hw/qdev.h" 25 #include "sysemu/dma.h" 26 #include "hw/i386/x86-iommu.h" 27 #include "hw/i386/ioapic.h" 28 #include "hw/pci/msi.h" 29 #include "hw/sysbus.h" 30 31 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" 32 #define INTEL_IOMMU_DEVICE(obj) \ 33 OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) 34 35 /* DMAR Hardware Unit Definition address (IOMMU unit) */ 36 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL 37 38 #define VTD_PCI_BUS_MAX 256 39 #define VTD_PCI_SLOT_MAX 32 40 #define VTD_PCI_FUNC_MAX 8 41 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 42 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) 43 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff) 44 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) 45 46 #define DMAR_REG_SIZE 0x230 47 #define VTD_HOST_ADDRESS_WIDTH 39 48 #define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1) 49 50 #define DMAR_REPORT_F_INTR (1) 51 52 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) 53 #define VTD_MSI_ADDR_HI_SHIFT (32) 54 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) 55 56 typedef struct VTDContextEntry VTDContextEntry; 57 typedef struct VTDContextCacheEntry VTDContextCacheEntry; 58 typedef struct IntelIOMMUState IntelIOMMUState; 59 typedef struct VTDAddressSpace VTDAddressSpace; 60 typedef struct VTDIOTLBEntry VTDIOTLBEntry; 61 typedef struct VTDBus VTDBus; 62 typedef union VTD_IR_TableEntry VTD_IR_TableEntry; 63 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; 64 typedef struct VTDIrq VTDIrq; 65 typedef struct VTD_MSIMessage VTD_MSIMessage; 66 67 /* Context-Entry */ 68 struct VTDContextEntry { 69 uint64_t lo; 70 uint64_t hi; 71 }; 72 73 struct VTDContextCacheEntry { 74 /* The cache entry is obsolete if 75 * context_cache_gen!=IntelIOMMUState.context_cache_gen 76 */ 77 uint32_t context_cache_gen; 78 struct VTDContextEntry context_entry; 79 }; 80 81 struct VTDAddressSpace { 82 PCIBus *bus; 83 uint8_t devfn; 84 AddressSpace as; 85 MemoryRegion iommu; 86 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ 87 IntelIOMMUState *iommu_state; 88 VTDContextCacheEntry context_cache_entry; 89 }; 90 91 struct VTDBus { 92 PCIBus* bus; /* A reference to the bus to provide translation for */ 93 VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */ 94 }; 95 96 struct VTDIOTLBEntry { 97 uint64_t gfn; 98 uint16_t domain_id; 99 uint64_t slpte; 100 uint64_t mask; 101 bool read_flags; 102 bool write_flags; 103 }; 104 105 /* VT-d Source-ID Qualifier types */ 106 enum { 107 VTD_SQ_FULL = 0x00, /* Full SID verification */ 108 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */ 109 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */ 110 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */ 111 VTD_SQ_MAX, 112 }; 113 114 /* VT-d Source Validation Types */ 115 enum { 116 VTD_SVT_NONE = 0x00, /* No validation */ 117 VTD_SVT_ALL = 0x01, /* Do full validation */ 118 VTD_SVT_BUS = 0x02, /* Validate bus range */ 119 VTD_SVT_MAX, 120 }; 121 122 /* Interrupt Remapping Table Entry Definition */ 123 union VTD_IR_TableEntry { 124 struct { 125 #ifdef HOST_WORDS_BIGENDIAN 126 uint32_t __reserved_1:8; /* Reserved 1 */ 127 uint32_t vector:8; /* Interrupt Vector */ 128 uint32_t irte_mode:1; /* IRTE Mode */ 129 uint32_t __reserved_0:3; /* Reserved 0 */ 130 uint32_t __avail:4; /* Available spaces for software */ 131 uint32_t delivery_mode:3; /* Delivery Mode */ 132 uint32_t trigger_mode:1; /* Trigger Mode */ 133 uint32_t redir_hint:1; /* Redirection Hint */ 134 uint32_t dest_mode:1; /* Destination Mode */ 135 uint32_t fault_disable:1; /* Fault Processing Disable */ 136 uint32_t present:1; /* Whether entry present/available */ 137 #else 138 uint32_t present:1; /* Whether entry present/available */ 139 uint32_t fault_disable:1; /* Fault Processing Disable */ 140 uint32_t dest_mode:1; /* Destination Mode */ 141 uint32_t redir_hint:1; /* Redirection Hint */ 142 uint32_t trigger_mode:1; /* Trigger Mode */ 143 uint32_t delivery_mode:3; /* Delivery Mode */ 144 uint32_t __avail:4; /* Available spaces for software */ 145 uint32_t __reserved_0:3; /* Reserved 0 */ 146 uint32_t irte_mode:1; /* IRTE Mode */ 147 uint32_t vector:8; /* Interrupt Vector */ 148 uint32_t __reserved_1:8; /* Reserved 1 */ 149 #endif 150 uint32_t dest_id; /* Destination ID */ 151 uint16_t source_id; /* Source-ID */ 152 #ifdef HOST_WORDS_BIGENDIAN 153 uint64_t __reserved_2:44; /* Reserved 2 */ 154 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 155 uint64_t sid_q:2; /* Source-ID Qualifier */ 156 #else 157 uint64_t sid_q:2; /* Source-ID Qualifier */ 158 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 159 uint64_t __reserved_2:44; /* Reserved 2 */ 160 #endif 161 } QEMU_PACKED irte; 162 uint64_t data[2]; 163 }; 164 165 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */ 166 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */ 167 168 /* Programming format for MSI/MSI-X addresses */ 169 union VTD_IR_MSIAddress { 170 struct { 171 #ifdef HOST_WORDS_BIGENDIAN 172 uint32_t __head:12; /* Should always be: 0x0fee */ 173 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 174 uint32_t int_mode:1; /* Interrupt format */ 175 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 176 uint32_t index_h:1; /* Interrupt index bit 15 */ 177 uint32_t __not_care:2; 178 #else 179 uint32_t __not_care:2; 180 uint32_t index_h:1; /* Interrupt index bit 15 */ 181 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 182 uint32_t int_mode:1; /* Interrupt format */ 183 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 184 uint32_t __head:12; /* Should always be: 0x0fee */ 185 #endif 186 } QEMU_PACKED addr; 187 uint32_t data; 188 }; 189 190 /* Generic IRQ entry information */ 191 struct VTDIrq { 192 /* Used by both IOAPIC/MSI interrupt remapping */ 193 uint8_t trigger_mode; 194 uint8_t vector; 195 uint8_t delivery_mode; 196 uint32_t dest; 197 uint8_t dest_mode; 198 199 /* only used by MSI interrupt remapping */ 200 uint8_t redir_hint; 201 uint8_t msi_addr_last_bits; 202 }; 203 204 struct VTD_MSIMessage { 205 union { 206 struct { 207 #ifdef HOST_WORDS_BIGENDIAN 208 uint32_t __addr_head:12; /* 0xfee */ 209 uint32_t dest:8; 210 uint32_t __reserved:8; 211 uint32_t redir_hint:1; 212 uint32_t dest_mode:1; 213 uint32_t __not_used:2; 214 #else 215 uint32_t __not_used:2; 216 uint32_t dest_mode:1; 217 uint32_t redir_hint:1; 218 uint32_t __reserved:8; 219 uint32_t dest:8; 220 uint32_t __addr_head:12; /* 0xfee */ 221 #endif 222 uint32_t __addr_hi; 223 } QEMU_PACKED; 224 uint64_t msi_addr; 225 }; 226 union { 227 struct { 228 #ifdef HOST_WORDS_BIGENDIAN 229 uint16_t trigger_mode:1; 230 uint16_t level:1; 231 uint16_t __resved:3; 232 uint16_t delivery_mode:3; 233 uint16_t vector:8; 234 #else 235 uint16_t vector:8; 236 uint16_t delivery_mode:3; 237 uint16_t __resved:3; 238 uint16_t level:1; 239 uint16_t trigger_mode:1; 240 #endif 241 uint16_t __resved1; 242 } QEMU_PACKED; 243 uint32_t msi_data; 244 }; 245 }; 246 247 /* When IR is enabled, all MSI/MSI-X data bits should be zero */ 248 #define VTD_IR_MSI_DATA (0) 249 250 /* The iommu (DMAR) device state struct */ 251 struct IntelIOMMUState { 252 X86IOMMUState x86_iommu; 253 MemoryRegion csrmem; 254 uint8_t csr[DMAR_REG_SIZE]; /* register values */ 255 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ 256 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ 257 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ 258 uint32_t version; 259 260 bool caching_mode; /* RO - is cap CM enabled? */ 261 262 dma_addr_t root; /* Current root table pointer */ 263 bool root_extended; /* Type of root table (extended or not) */ 264 bool dmar_enabled; /* Set if DMA remapping is enabled */ 265 266 uint16_t iq_head; /* Current invalidation queue head */ 267 uint16_t iq_tail; /* Current invalidation queue tail */ 268 dma_addr_t iq; /* Current invalidation queue pointer */ 269 uint16_t iq_size; /* IQ Size in number of entries */ 270 bool qi_enabled; /* Set if the QI is enabled */ 271 uint8_t iq_last_desc_type; /* The type of last completed descriptor */ 272 273 /* The index of the Fault Recording Register to be used next. 274 * Wraps around from N-1 to 0, where N is the number of FRCD_REG. 275 */ 276 uint16_t next_frcd_reg; 277 278 uint64_t cap; /* The value of capability reg */ 279 uint64_t ecap; /* The value of extended capability reg */ 280 281 uint32_t context_cache_gen; /* Should be in [1,MAX] */ 282 GHashTable *iotlb; /* IOTLB */ 283 284 MemoryRegionIOMMUOps iommu_ops; 285 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */ 286 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */ 287 288 /* interrupt remapping */ 289 bool intr_enabled; /* Whether guest enabled IR */ 290 dma_addr_t intr_root; /* Interrupt remapping table pointer */ 291 uint32_t intr_size; /* Number of IR table entries */ 292 bool intr_eime; /* Extended interrupt mode enabled */ 293 OnOffAuto intr_eim; /* Toggle for EIM cabability */ 294 bool buggy_eim; /* Force buggy EIM unless eim=off */ 295 }; 296 297 /* Find the VTD Address space associated with the given bus pointer, 298 * create a new one if none exists 299 */ 300 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn); 301 302 #endif 303