1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef INTEL_IOMMU_H 23 #define INTEL_IOMMU_H 24 25 #include "hw/i386/x86-iommu.h" 26 #include "qemu/iova-tree.h" 27 #include "qom/object.h" 28 29 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" 30 typedef struct IntelIOMMUState IntelIOMMUState; 31 DECLARE_INSTANCE_CHECKER(IntelIOMMUState, INTEL_IOMMU_DEVICE, 32 TYPE_INTEL_IOMMU_DEVICE) 33 34 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region" 35 36 /* DMAR Hardware Unit Definition address (IOMMU unit) */ 37 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL 38 39 #define VTD_PCI_BUS_MAX 256 40 #define VTD_PCI_SLOT_MAX 32 41 #define VTD_PCI_FUNC_MAX 8 42 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 43 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) 44 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff) 45 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) 46 47 #define DMAR_REG_SIZE 0x230 48 #define VTD_HOST_AW_39BIT 39 49 #define VTD_HOST_AW_48BIT 48 50 #define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT 51 #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) 52 53 #define DMAR_REPORT_F_INTR (1) 54 55 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) 56 #define VTD_MSI_ADDR_HI_SHIFT (32) 57 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) 58 59 typedef struct VTDContextEntry VTDContextEntry; 60 typedef struct VTDContextCacheEntry VTDContextCacheEntry; 61 typedef struct VTDAddressSpace VTDAddressSpace; 62 typedef struct VTDIOTLBEntry VTDIOTLBEntry; 63 typedef struct VTDBus VTDBus; 64 typedef union VTD_IR_TableEntry VTD_IR_TableEntry; 65 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; 66 typedef struct VTDPASIDDirEntry VTDPASIDDirEntry; 67 typedef struct VTDPASIDEntry VTDPASIDEntry; 68 69 /* Context-Entry */ 70 struct VTDContextEntry { 71 union { 72 struct { 73 uint64_t lo; 74 uint64_t hi; 75 }; 76 struct { 77 uint64_t val[4]; 78 }; 79 }; 80 }; 81 82 struct VTDContextCacheEntry { 83 /* The cache entry is obsolete if 84 * context_cache_gen!=IntelIOMMUState.context_cache_gen 85 */ 86 uint32_t context_cache_gen; 87 struct VTDContextEntry context_entry; 88 }; 89 90 /* PASID Directory Entry */ 91 struct VTDPASIDDirEntry { 92 uint64_t val; 93 }; 94 95 /* PASID Table Entry */ 96 struct VTDPASIDEntry { 97 uint64_t val[8]; 98 }; 99 100 struct VTDAddressSpace { 101 PCIBus *bus; 102 uint8_t devfn; 103 AddressSpace as; 104 IOMMUMemoryRegion iommu; 105 MemoryRegion root; /* The root container of the device */ 106 MemoryRegion nodmar; /* The alias of shared nodmar MR */ 107 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ 108 IntelIOMMUState *iommu_state; 109 VTDContextCacheEntry context_cache_entry; 110 QLIST_ENTRY(VTDAddressSpace) next; 111 /* Superset of notifier flags that this address space has */ 112 IOMMUNotifierFlag notifier_flags; 113 IOVATree *iova_tree; /* Traces mapped IOVA ranges */ 114 }; 115 116 struct VTDBus { 117 PCIBus* bus; /* A reference to the bus to provide translation for */ 118 /* A table of VTDAddressSpace objects indexed by devfn */ 119 VTDAddressSpace *dev_as[]; 120 }; 121 122 struct VTDIOTLBEntry { 123 uint64_t gfn; 124 uint16_t domain_id; 125 uint64_t slpte; 126 uint64_t mask; 127 uint8_t access_flags; 128 }; 129 130 /* VT-d Source-ID Qualifier types */ 131 enum { 132 VTD_SQ_FULL = 0x00, /* Full SID verification */ 133 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */ 134 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */ 135 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */ 136 VTD_SQ_MAX, 137 }; 138 139 /* VT-d Source Validation Types */ 140 enum { 141 VTD_SVT_NONE = 0x00, /* No validation */ 142 VTD_SVT_ALL = 0x01, /* Do full validation */ 143 VTD_SVT_BUS = 0x02, /* Validate bus range */ 144 VTD_SVT_MAX, 145 }; 146 147 /* Interrupt Remapping Table Entry Definition */ 148 union VTD_IR_TableEntry { 149 struct { 150 #ifdef HOST_WORDS_BIGENDIAN 151 uint32_t __reserved_1:8; /* Reserved 1 */ 152 uint32_t vector:8; /* Interrupt Vector */ 153 uint32_t irte_mode:1; /* IRTE Mode */ 154 uint32_t __reserved_0:3; /* Reserved 0 */ 155 uint32_t __avail:4; /* Available spaces for software */ 156 uint32_t delivery_mode:3; /* Delivery Mode */ 157 uint32_t trigger_mode:1; /* Trigger Mode */ 158 uint32_t redir_hint:1; /* Redirection Hint */ 159 uint32_t dest_mode:1; /* Destination Mode */ 160 uint32_t fault_disable:1; /* Fault Processing Disable */ 161 uint32_t present:1; /* Whether entry present/available */ 162 #else 163 uint32_t present:1; /* Whether entry present/available */ 164 uint32_t fault_disable:1; /* Fault Processing Disable */ 165 uint32_t dest_mode:1; /* Destination Mode */ 166 uint32_t redir_hint:1; /* Redirection Hint */ 167 uint32_t trigger_mode:1; /* Trigger Mode */ 168 uint32_t delivery_mode:3; /* Delivery Mode */ 169 uint32_t __avail:4; /* Available spaces for software */ 170 uint32_t __reserved_0:3; /* Reserved 0 */ 171 uint32_t irte_mode:1; /* IRTE Mode */ 172 uint32_t vector:8; /* Interrupt Vector */ 173 uint32_t __reserved_1:8; /* Reserved 1 */ 174 #endif 175 uint32_t dest_id; /* Destination ID */ 176 uint16_t source_id; /* Source-ID */ 177 #ifdef HOST_WORDS_BIGENDIAN 178 uint64_t __reserved_2:44; /* Reserved 2 */ 179 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 180 uint64_t sid_q:2; /* Source-ID Qualifier */ 181 #else 182 uint64_t sid_q:2; /* Source-ID Qualifier */ 183 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 184 uint64_t __reserved_2:44; /* Reserved 2 */ 185 #endif 186 } QEMU_PACKED irte; 187 uint64_t data[2]; 188 }; 189 190 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */ 191 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */ 192 193 /* Programming format for MSI/MSI-X addresses */ 194 union VTD_IR_MSIAddress { 195 struct { 196 #ifdef HOST_WORDS_BIGENDIAN 197 uint32_t __head:12; /* Should always be: 0x0fee */ 198 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 199 uint32_t int_mode:1; /* Interrupt format */ 200 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 201 uint32_t index_h:1; /* Interrupt index bit 15 */ 202 uint32_t __not_care:2; 203 #else 204 uint32_t __not_care:2; 205 uint32_t index_h:1; /* Interrupt index bit 15 */ 206 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 207 uint32_t int_mode:1; /* Interrupt format */ 208 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 209 uint32_t __head:12; /* Should always be: 0x0fee */ 210 #endif 211 } QEMU_PACKED addr; 212 uint32_t data; 213 }; 214 215 /* When IR is enabled, all MSI/MSI-X data bits should be zero */ 216 #define VTD_IR_MSI_DATA (0) 217 218 /* The iommu (DMAR) device state struct */ 219 struct IntelIOMMUState { 220 X86IOMMUState x86_iommu; 221 MemoryRegion csrmem; 222 MemoryRegion mr_nodmar; 223 MemoryRegion mr_ir; 224 MemoryRegion mr_sys_alias; 225 uint8_t csr[DMAR_REG_SIZE]; /* register values */ 226 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ 227 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ 228 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ 229 uint32_t version; 230 231 bool caching_mode; /* RO - is cap CM enabled? */ 232 bool scalable_mode; /* RO - is Scalable Mode supported? */ 233 234 dma_addr_t root; /* Current root table pointer */ 235 bool root_scalable; /* Type of root table (scalable or not) */ 236 bool dmar_enabled; /* Set if DMA remapping is enabled */ 237 238 uint16_t iq_head; /* Current invalidation queue head */ 239 uint16_t iq_tail; /* Current invalidation queue tail */ 240 dma_addr_t iq; /* Current invalidation queue pointer */ 241 uint16_t iq_size; /* IQ Size in number of entries */ 242 bool iq_dw; /* IQ descriptor width 256bit or not */ 243 bool qi_enabled; /* Set if the QI is enabled */ 244 uint8_t iq_last_desc_type; /* The type of last completed descriptor */ 245 246 /* The index of the Fault Recording Register to be used next. 247 * Wraps around from N-1 to 0, where N is the number of FRCD_REG. 248 */ 249 uint16_t next_frcd_reg; 250 251 uint64_t cap; /* The value of capability reg */ 252 uint64_t ecap; /* The value of extended capability reg */ 253 254 uint32_t context_cache_gen; /* Should be in [1,MAX] */ 255 GHashTable *iotlb; /* IOTLB */ 256 257 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */ 258 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */ 259 /* list of registered notifiers */ 260 QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; 261 262 /* interrupt remapping */ 263 bool intr_enabled; /* Whether guest enabled IR */ 264 dma_addr_t intr_root; /* Interrupt remapping table pointer */ 265 uint32_t intr_size; /* Number of IR table entries */ 266 bool intr_eime; /* Extended interrupt mode enabled */ 267 OnOffAuto intr_eim; /* Toggle for EIM cabability */ 268 bool buggy_eim; /* Force buggy EIM unless eim=off */ 269 uint8_t aw_bits; /* Host/IOVA address width (in bits) */ 270 bool dma_drain; /* Whether DMA r/w draining enabled */ 271 272 /* 273 * Protects IOMMU states in general. Currently it protects the 274 * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace. 275 */ 276 QemuMutex iommu_lock; 277 }; 278 279 /* Find the VTD Address space associated with the given bus pointer, 280 * create a new one if none exists 281 */ 282 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn); 283 284 #endif 285