1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef INTEL_IOMMU_H 23 #define INTEL_IOMMU_H 24 #include "hw/qdev.h" 25 #include "sysemu/dma.h" 26 #include "hw/i386/x86-iommu.h" 27 #include "hw/i386/ioapic.h" 28 #include "hw/pci/msi.h" 29 #include "hw/sysbus.h" 30 31 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" 32 #define INTEL_IOMMU_DEVICE(obj) \ 33 OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) 34 35 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region" 36 37 /* DMAR Hardware Unit Definition address (IOMMU unit) */ 38 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL 39 40 #define VTD_PCI_BUS_MAX 256 41 #define VTD_PCI_SLOT_MAX 32 42 #define VTD_PCI_FUNC_MAX 8 43 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 44 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) 45 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff) 46 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) 47 48 #define DMAR_REG_SIZE 0x230 49 #define VTD_HOST_ADDRESS_WIDTH 39 50 #define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1) 51 52 #define DMAR_REPORT_F_INTR (1) 53 54 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) 55 #define VTD_MSI_ADDR_HI_SHIFT (32) 56 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) 57 58 typedef struct VTDContextEntry VTDContextEntry; 59 typedef struct VTDContextCacheEntry VTDContextCacheEntry; 60 typedef struct IntelIOMMUState IntelIOMMUState; 61 typedef struct VTDAddressSpace VTDAddressSpace; 62 typedef struct VTDIOTLBEntry VTDIOTLBEntry; 63 typedef struct VTDBus VTDBus; 64 typedef union VTD_IR_TableEntry VTD_IR_TableEntry; 65 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; 66 typedef struct VTDIrq VTDIrq; 67 typedef struct VTD_MSIMessage VTD_MSIMessage; 68 typedef struct IntelIOMMUNotifierNode IntelIOMMUNotifierNode; 69 70 /* Context-Entry */ 71 struct VTDContextEntry { 72 uint64_t lo; 73 uint64_t hi; 74 }; 75 76 struct VTDContextCacheEntry { 77 /* The cache entry is obsolete if 78 * context_cache_gen!=IntelIOMMUState.context_cache_gen 79 */ 80 uint32_t context_cache_gen; 81 struct VTDContextEntry context_entry; 82 }; 83 84 struct VTDAddressSpace { 85 PCIBus *bus; 86 uint8_t devfn; 87 AddressSpace as; 88 IOMMUMemoryRegion iommu; 89 MemoryRegion root; 90 MemoryRegion sys_alias; 91 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ 92 IntelIOMMUState *iommu_state; 93 VTDContextCacheEntry context_cache_entry; 94 }; 95 96 struct VTDBus { 97 PCIBus* bus; /* A reference to the bus to provide translation for */ 98 VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */ 99 }; 100 101 struct VTDIOTLBEntry { 102 uint64_t gfn; 103 uint16_t domain_id; 104 uint64_t slpte; 105 uint64_t mask; 106 uint8_t access_flags; 107 }; 108 109 /* VT-d Source-ID Qualifier types */ 110 enum { 111 VTD_SQ_FULL = 0x00, /* Full SID verification */ 112 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */ 113 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */ 114 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */ 115 VTD_SQ_MAX, 116 }; 117 118 /* VT-d Source Validation Types */ 119 enum { 120 VTD_SVT_NONE = 0x00, /* No validation */ 121 VTD_SVT_ALL = 0x01, /* Do full validation */ 122 VTD_SVT_BUS = 0x02, /* Validate bus range */ 123 VTD_SVT_MAX, 124 }; 125 126 /* Interrupt Remapping Table Entry Definition */ 127 union VTD_IR_TableEntry { 128 struct { 129 #ifdef HOST_WORDS_BIGENDIAN 130 uint32_t __reserved_1:8; /* Reserved 1 */ 131 uint32_t vector:8; /* Interrupt Vector */ 132 uint32_t irte_mode:1; /* IRTE Mode */ 133 uint32_t __reserved_0:3; /* Reserved 0 */ 134 uint32_t __avail:4; /* Available spaces for software */ 135 uint32_t delivery_mode:3; /* Delivery Mode */ 136 uint32_t trigger_mode:1; /* Trigger Mode */ 137 uint32_t redir_hint:1; /* Redirection Hint */ 138 uint32_t dest_mode:1; /* Destination Mode */ 139 uint32_t fault_disable:1; /* Fault Processing Disable */ 140 uint32_t present:1; /* Whether entry present/available */ 141 #else 142 uint32_t present:1; /* Whether entry present/available */ 143 uint32_t fault_disable:1; /* Fault Processing Disable */ 144 uint32_t dest_mode:1; /* Destination Mode */ 145 uint32_t redir_hint:1; /* Redirection Hint */ 146 uint32_t trigger_mode:1; /* Trigger Mode */ 147 uint32_t delivery_mode:3; /* Delivery Mode */ 148 uint32_t __avail:4; /* Available spaces for software */ 149 uint32_t __reserved_0:3; /* Reserved 0 */ 150 uint32_t irte_mode:1; /* IRTE Mode */ 151 uint32_t vector:8; /* Interrupt Vector */ 152 uint32_t __reserved_1:8; /* Reserved 1 */ 153 #endif 154 uint32_t dest_id; /* Destination ID */ 155 uint16_t source_id; /* Source-ID */ 156 #ifdef HOST_WORDS_BIGENDIAN 157 uint64_t __reserved_2:44; /* Reserved 2 */ 158 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 159 uint64_t sid_q:2; /* Source-ID Qualifier */ 160 #else 161 uint64_t sid_q:2; /* Source-ID Qualifier */ 162 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 163 uint64_t __reserved_2:44; /* Reserved 2 */ 164 #endif 165 } QEMU_PACKED irte; 166 uint64_t data[2]; 167 }; 168 169 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */ 170 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */ 171 172 /* Programming format for MSI/MSI-X addresses */ 173 union VTD_IR_MSIAddress { 174 struct { 175 #ifdef HOST_WORDS_BIGENDIAN 176 uint32_t __head:12; /* Should always be: 0x0fee */ 177 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 178 uint32_t int_mode:1; /* Interrupt format */ 179 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 180 uint32_t index_h:1; /* Interrupt index bit 15 */ 181 uint32_t __not_care:2; 182 #else 183 uint32_t __not_care:2; 184 uint32_t index_h:1; /* Interrupt index bit 15 */ 185 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 186 uint32_t int_mode:1; /* Interrupt format */ 187 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 188 uint32_t __head:12; /* Should always be: 0x0fee */ 189 #endif 190 } QEMU_PACKED addr; 191 uint32_t data; 192 }; 193 194 /* Generic IRQ entry information */ 195 struct VTDIrq { 196 /* Used by both IOAPIC/MSI interrupt remapping */ 197 uint8_t trigger_mode; 198 uint8_t vector; 199 uint8_t delivery_mode; 200 uint32_t dest; 201 uint8_t dest_mode; 202 203 /* only used by MSI interrupt remapping */ 204 uint8_t redir_hint; 205 uint8_t msi_addr_last_bits; 206 }; 207 208 struct VTD_MSIMessage { 209 union { 210 struct { 211 #ifdef HOST_WORDS_BIGENDIAN 212 uint32_t __addr_head:12; /* 0xfee */ 213 uint32_t dest:8; 214 uint32_t __reserved:8; 215 uint32_t redir_hint:1; 216 uint32_t dest_mode:1; 217 uint32_t __not_used:2; 218 #else 219 uint32_t __not_used:2; 220 uint32_t dest_mode:1; 221 uint32_t redir_hint:1; 222 uint32_t __reserved:8; 223 uint32_t dest:8; 224 uint32_t __addr_head:12; /* 0xfee */ 225 #endif 226 uint32_t __addr_hi; 227 } QEMU_PACKED; 228 uint64_t msi_addr; 229 }; 230 union { 231 struct { 232 #ifdef HOST_WORDS_BIGENDIAN 233 uint16_t trigger_mode:1; 234 uint16_t level:1; 235 uint16_t __resved:3; 236 uint16_t delivery_mode:3; 237 uint16_t vector:8; 238 #else 239 uint16_t vector:8; 240 uint16_t delivery_mode:3; 241 uint16_t __resved:3; 242 uint16_t level:1; 243 uint16_t trigger_mode:1; 244 #endif 245 uint16_t __resved1; 246 } QEMU_PACKED; 247 uint32_t msi_data; 248 }; 249 }; 250 251 /* When IR is enabled, all MSI/MSI-X data bits should be zero */ 252 #define VTD_IR_MSI_DATA (0) 253 254 struct IntelIOMMUNotifierNode { 255 VTDAddressSpace *vtd_as; 256 QLIST_ENTRY(IntelIOMMUNotifierNode) next; 257 }; 258 259 /* The iommu (DMAR) device state struct */ 260 struct IntelIOMMUState { 261 X86IOMMUState x86_iommu; 262 MemoryRegion csrmem; 263 uint8_t csr[DMAR_REG_SIZE]; /* register values */ 264 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ 265 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ 266 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ 267 uint32_t version; 268 269 bool caching_mode; /* RO - is cap CM enabled? */ 270 271 dma_addr_t root; /* Current root table pointer */ 272 bool root_extended; /* Type of root table (extended or not) */ 273 bool dmar_enabled; /* Set if DMA remapping is enabled */ 274 275 uint16_t iq_head; /* Current invalidation queue head */ 276 uint16_t iq_tail; /* Current invalidation queue tail */ 277 dma_addr_t iq; /* Current invalidation queue pointer */ 278 uint16_t iq_size; /* IQ Size in number of entries */ 279 bool qi_enabled; /* Set if the QI is enabled */ 280 uint8_t iq_last_desc_type; /* The type of last completed descriptor */ 281 282 /* The index of the Fault Recording Register to be used next. 283 * Wraps around from N-1 to 0, where N is the number of FRCD_REG. 284 */ 285 uint16_t next_frcd_reg; 286 287 uint64_t cap; /* The value of capability reg */ 288 uint64_t ecap; /* The value of extended capability reg */ 289 290 uint32_t context_cache_gen; /* Should be in [1,MAX] */ 291 GHashTable *iotlb; /* IOTLB */ 292 293 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */ 294 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */ 295 /* list of registered notifiers */ 296 QLIST_HEAD(, IntelIOMMUNotifierNode) notifiers_list; 297 298 /* interrupt remapping */ 299 bool intr_enabled; /* Whether guest enabled IR */ 300 dma_addr_t intr_root; /* Interrupt remapping table pointer */ 301 uint32_t intr_size; /* Number of IR table entries */ 302 bool intr_eime; /* Extended interrupt mode enabled */ 303 OnOffAuto intr_eim; /* Toggle for EIM cabability */ 304 bool buggy_eim; /* Force buggy EIM unless eim=off */ 305 }; 306 307 /* Find the VTD Address space associated with the given bus pointer, 308 * create a new one if none exists 309 */ 310 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn); 311 312 #endif 313