1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef INTEL_IOMMU_H 23 #define INTEL_IOMMU_H 24 #include "hw/qdev.h" 25 #include "sysemu/dma.h" 26 #include "hw/i386/x86-iommu.h" 27 #include "hw/i386/ioapic.h" 28 #include "hw/pci/msi.h" 29 #include "hw/sysbus.h" 30 31 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" 32 #define INTEL_IOMMU_DEVICE(obj) \ 33 OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) 34 35 /* DMAR Hardware Unit Definition address (IOMMU unit) */ 36 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL 37 38 #define VTD_PCI_BUS_MAX 256 39 #define VTD_PCI_SLOT_MAX 32 40 #define VTD_PCI_FUNC_MAX 8 41 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 42 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) 43 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff) 44 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) 45 46 #define DMAR_REG_SIZE 0x230 47 #define VTD_HOST_ADDRESS_WIDTH 39 48 #define VTD_HAW_MASK ((1ULL << VTD_HOST_ADDRESS_WIDTH) - 1) 49 50 #define DMAR_REPORT_F_INTR (1) 51 52 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) 53 #define VTD_MSI_ADDR_HI_SHIFT (32) 54 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) 55 56 typedef struct VTDContextEntry VTDContextEntry; 57 typedef struct VTDContextCacheEntry VTDContextCacheEntry; 58 typedef struct IntelIOMMUState IntelIOMMUState; 59 typedef struct VTDAddressSpace VTDAddressSpace; 60 typedef struct VTDIOTLBEntry VTDIOTLBEntry; 61 typedef struct VTDBus VTDBus; 62 typedef union VTD_IR_TableEntry VTD_IR_TableEntry; 63 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; 64 typedef struct VTDIrq VTDIrq; 65 typedef struct VTD_MSIMessage VTD_MSIMessage; 66 typedef struct IntelIOMMUNotifierNode IntelIOMMUNotifierNode; 67 68 /* Context-Entry */ 69 struct VTDContextEntry { 70 uint64_t lo; 71 uint64_t hi; 72 }; 73 74 struct VTDContextCacheEntry { 75 /* The cache entry is obsolete if 76 * context_cache_gen!=IntelIOMMUState.context_cache_gen 77 */ 78 uint32_t context_cache_gen; 79 struct VTDContextEntry context_entry; 80 }; 81 82 struct VTDAddressSpace { 83 PCIBus *bus; 84 uint8_t devfn; 85 AddressSpace as; 86 MemoryRegion iommu; 87 MemoryRegion root; 88 MemoryRegion sys_alias; 89 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ 90 IntelIOMMUState *iommu_state; 91 VTDContextCacheEntry context_cache_entry; 92 }; 93 94 struct VTDBus { 95 PCIBus* bus; /* A reference to the bus to provide translation for */ 96 VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */ 97 }; 98 99 struct VTDIOTLBEntry { 100 uint64_t gfn; 101 uint16_t domain_id; 102 uint64_t slpte; 103 uint64_t mask; 104 bool read_flags; 105 bool write_flags; 106 }; 107 108 /* VT-d Source-ID Qualifier types */ 109 enum { 110 VTD_SQ_FULL = 0x00, /* Full SID verification */ 111 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */ 112 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */ 113 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */ 114 VTD_SQ_MAX, 115 }; 116 117 /* VT-d Source Validation Types */ 118 enum { 119 VTD_SVT_NONE = 0x00, /* No validation */ 120 VTD_SVT_ALL = 0x01, /* Do full validation */ 121 VTD_SVT_BUS = 0x02, /* Validate bus range */ 122 VTD_SVT_MAX, 123 }; 124 125 /* Interrupt Remapping Table Entry Definition */ 126 union VTD_IR_TableEntry { 127 struct { 128 #ifdef HOST_WORDS_BIGENDIAN 129 uint32_t __reserved_1:8; /* Reserved 1 */ 130 uint32_t vector:8; /* Interrupt Vector */ 131 uint32_t irte_mode:1; /* IRTE Mode */ 132 uint32_t __reserved_0:3; /* Reserved 0 */ 133 uint32_t __avail:4; /* Available spaces for software */ 134 uint32_t delivery_mode:3; /* Delivery Mode */ 135 uint32_t trigger_mode:1; /* Trigger Mode */ 136 uint32_t redir_hint:1; /* Redirection Hint */ 137 uint32_t dest_mode:1; /* Destination Mode */ 138 uint32_t fault_disable:1; /* Fault Processing Disable */ 139 uint32_t present:1; /* Whether entry present/available */ 140 #else 141 uint32_t present:1; /* Whether entry present/available */ 142 uint32_t fault_disable:1; /* Fault Processing Disable */ 143 uint32_t dest_mode:1; /* Destination Mode */ 144 uint32_t redir_hint:1; /* Redirection Hint */ 145 uint32_t trigger_mode:1; /* Trigger Mode */ 146 uint32_t delivery_mode:3; /* Delivery Mode */ 147 uint32_t __avail:4; /* Available spaces for software */ 148 uint32_t __reserved_0:3; /* Reserved 0 */ 149 uint32_t irte_mode:1; /* IRTE Mode */ 150 uint32_t vector:8; /* Interrupt Vector */ 151 uint32_t __reserved_1:8; /* Reserved 1 */ 152 #endif 153 uint32_t dest_id; /* Destination ID */ 154 uint16_t source_id; /* Source-ID */ 155 #ifdef HOST_WORDS_BIGENDIAN 156 uint64_t __reserved_2:44; /* Reserved 2 */ 157 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 158 uint64_t sid_q:2; /* Source-ID Qualifier */ 159 #else 160 uint64_t sid_q:2; /* Source-ID Qualifier */ 161 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 162 uint64_t __reserved_2:44; /* Reserved 2 */ 163 #endif 164 } QEMU_PACKED irte; 165 uint64_t data[2]; 166 }; 167 168 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */ 169 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */ 170 171 /* Programming format for MSI/MSI-X addresses */ 172 union VTD_IR_MSIAddress { 173 struct { 174 #ifdef HOST_WORDS_BIGENDIAN 175 uint32_t __head:12; /* Should always be: 0x0fee */ 176 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 177 uint32_t int_mode:1; /* Interrupt format */ 178 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 179 uint32_t index_h:1; /* Interrupt index bit 15 */ 180 uint32_t __not_care:2; 181 #else 182 uint32_t __not_care:2; 183 uint32_t index_h:1; /* Interrupt index bit 15 */ 184 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 185 uint32_t int_mode:1; /* Interrupt format */ 186 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 187 uint32_t __head:12; /* Should always be: 0x0fee */ 188 #endif 189 } QEMU_PACKED addr; 190 uint32_t data; 191 }; 192 193 /* Generic IRQ entry information */ 194 struct VTDIrq { 195 /* Used by both IOAPIC/MSI interrupt remapping */ 196 uint8_t trigger_mode; 197 uint8_t vector; 198 uint8_t delivery_mode; 199 uint32_t dest; 200 uint8_t dest_mode; 201 202 /* only used by MSI interrupt remapping */ 203 uint8_t redir_hint; 204 uint8_t msi_addr_last_bits; 205 }; 206 207 struct VTD_MSIMessage { 208 union { 209 struct { 210 #ifdef HOST_WORDS_BIGENDIAN 211 uint32_t __addr_head:12; /* 0xfee */ 212 uint32_t dest:8; 213 uint32_t __reserved:8; 214 uint32_t redir_hint:1; 215 uint32_t dest_mode:1; 216 uint32_t __not_used:2; 217 #else 218 uint32_t __not_used:2; 219 uint32_t dest_mode:1; 220 uint32_t redir_hint:1; 221 uint32_t __reserved:8; 222 uint32_t dest:8; 223 uint32_t __addr_head:12; /* 0xfee */ 224 #endif 225 uint32_t __addr_hi; 226 } QEMU_PACKED; 227 uint64_t msi_addr; 228 }; 229 union { 230 struct { 231 #ifdef HOST_WORDS_BIGENDIAN 232 uint16_t trigger_mode:1; 233 uint16_t level:1; 234 uint16_t __resved:3; 235 uint16_t delivery_mode:3; 236 uint16_t vector:8; 237 #else 238 uint16_t vector:8; 239 uint16_t delivery_mode:3; 240 uint16_t __resved:3; 241 uint16_t level:1; 242 uint16_t trigger_mode:1; 243 #endif 244 uint16_t __resved1; 245 } QEMU_PACKED; 246 uint32_t msi_data; 247 }; 248 }; 249 250 /* When IR is enabled, all MSI/MSI-X data bits should be zero */ 251 #define VTD_IR_MSI_DATA (0) 252 253 struct IntelIOMMUNotifierNode { 254 VTDAddressSpace *vtd_as; 255 QLIST_ENTRY(IntelIOMMUNotifierNode) next; 256 }; 257 258 /* The iommu (DMAR) device state struct */ 259 struct IntelIOMMUState { 260 X86IOMMUState x86_iommu; 261 MemoryRegion csrmem; 262 uint8_t csr[DMAR_REG_SIZE]; /* register values */ 263 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ 264 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ 265 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ 266 uint32_t version; 267 268 bool caching_mode; /* RO - is cap CM enabled? */ 269 270 dma_addr_t root; /* Current root table pointer */ 271 bool root_extended; /* Type of root table (extended or not) */ 272 bool dmar_enabled; /* Set if DMA remapping is enabled */ 273 274 uint16_t iq_head; /* Current invalidation queue head */ 275 uint16_t iq_tail; /* Current invalidation queue tail */ 276 dma_addr_t iq; /* Current invalidation queue pointer */ 277 uint16_t iq_size; /* IQ Size in number of entries */ 278 bool qi_enabled; /* Set if the QI is enabled */ 279 uint8_t iq_last_desc_type; /* The type of last completed descriptor */ 280 281 /* The index of the Fault Recording Register to be used next. 282 * Wraps around from N-1 to 0, where N is the number of FRCD_REG. 283 */ 284 uint16_t next_frcd_reg; 285 286 uint64_t cap; /* The value of capability reg */ 287 uint64_t ecap; /* The value of extended capability reg */ 288 289 uint32_t context_cache_gen; /* Should be in [1,MAX] */ 290 GHashTable *iotlb; /* IOTLB */ 291 292 MemoryRegionIOMMUOps iommu_ops; 293 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */ 294 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */ 295 /* list of registered notifiers */ 296 QLIST_HEAD(, IntelIOMMUNotifierNode) notifiers_list; 297 298 /* interrupt remapping */ 299 bool intr_enabled; /* Whether guest enabled IR */ 300 dma_addr_t intr_root; /* Interrupt remapping table pointer */ 301 uint32_t intr_size; /* Number of IR table entries */ 302 bool intr_eime; /* Extended interrupt mode enabled */ 303 OnOffAuto intr_eim; /* Toggle for EIM cabability */ 304 bool buggy_eim; /* Force buggy EIM unless eim=off */ 305 }; 306 307 /* Find the VTD Address space associated with the given bus pointer, 308 * create a new one if none exists 309 */ 310 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn); 311 312 #endif 313