1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef INTEL_IOMMU_H 23 #define INTEL_IOMMU_H 24 #include "hw/qdev.h" 25 #include "sysemu/dma.h" 26 #include "hw/i386/x86-iommu.h" 27 #include "hw/i386/ioapic.h" 28 #include "hw/pci/msi.h" 29 #include "hw/sysbus.h" 30 #include "qemu/iova-tree.h" 31 32 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" 33 #define INTEL_IOMMU_DEVICE(obj) \ 34 OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) 35 36 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region" 37 38 /* DMAR Hardware Unit Definition address (IOMMU unit) */ 39 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL 40 41 #define VTD_PCI_BUS_MAX 256 42 #define VTD_PCI_SLOT_MAX 32 43 #define VTD_PCI_FUNC_MAX 8 44 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 45 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) 46 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff) 47 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) 48 49 #define DMAR_REG_SIZE 0x230 50 #define VTD_HOST_AW_39BIT 39 51 #define VTD_HOST_AW_48BIT 48 52 #define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT 53 #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) 54 55 #define DMAR_REPORT_F_INTR (1) 56 57 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) 58 #define VTD_MSI_ADDR_HI_SHIFT (32) 59 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) 60 61 typedef struct VTDContextEntry VTDContextEntry; 62 typedef struct VTDContextCacheEntry VTDContextCacheEntry; 63 typedef struct IntelIOMMUState IntelIOMMUState; 64 typedef struct VTDAddressSpace VTDAddressSpace; 65 typedef struct VTDIOTLBEntry VTDIOTLBEntry; 66 typedef struct VTDBus VTDBus; 67 typedef union VTD_IR_TableEntry VTD_IR_TableEntry; 68 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; 69 70 /* Context-Entry */ 71 struct VTDContextEntry { 72 uint64_t lo; 73 uint64_t hi; 74 }; 75 76 struct VTDContextCacheEntry { 77 /* The cache entry is obsolete if 78 * context_cache_gen!=IntelIOMMUState.context_cache_gen 79 */ 80 uint32_t context_cache_gen; 81 struct VTDContextEntry context_entry; 82 }; 83 84 struct VTDAddressSpace { 85 PCIBus *bus; 86 uint8_t devfn; 87 AddressSpace as; 88 IOMMUMemoryRegion iommu; 89 MemoryRegion root; 90 MemoryRegion sys_alias; 91 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ 92 IntelIOMMUState *iommu_state; 93 VTDContextCacheEntry context_cache_entry; 94 QLIST_ENTRY(VTDAddressSpace) next; 95 /* Superset of notifier flags that this address space has */ 96 IOMMUNotifierFlag notifier_flags; 97 IOVATree *iova_tree; /* Traces mapped IOVA ranges */ 98 }; 99 100 struct VTDBus { 101 PCIBus* bus; /* A reference to the bus to provide translation for */ 102 VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */ 103 }; 104 105 struct VTDIOTLBEntry { 106 uint64_t gfn; 107 uint16_t domain_id; 108 uint64_t slpte; 109 uint64_t mask; 110 uint8_t access_flags; 111 }; 112 113 /* VT-d Source-ID Qualifier types */ 114 enum { 115 VTD_SQ_FULL = 0x00, /* Full SID verification */ 116 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */ 117 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */ 118 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */ 119 VTD_SQ_MAX, 120 }; 121 122 /* VT-d Source Validation Types */ 123 enum { 124 VTD_SVT_NONE = 0x00, /* No validation */ 125 VTD_SVT_ALL = 0x01, /* Do full validation */ 126 VTD_SVT_BUS = 0x02, /* Validate bus range */ 127 VTD_SVT_MAX, 128 }; 129 130 /* Interrupt Remapping Table Entry Definition */ 131 union VTD_IR_TableEntry { 132 struct { 133 #ifdef HOST_WORDS_BIGENDIAN 134 uint32_t __reserved_1:8; /* Reserved 1 */ 135 uint32_t vector:8; /* Interrupt Vector */ 136 uint32_t irte_mode:1; /* IRTE Mode */ 137 uint32_t __reserved_0:3; /* Reserved 0 */ 138 uint32_t __avail:4; /* Available spaces for software */ 139 uint32_t delivery_mode:3; /* Delivery Mode */ 140 uint32_t trigger_mode:1; /* Trigger Mode */ 141 uint32_t redir_hint:1; /* Redirection Hint */ 142 uint32_t dest_mode:1; /* Destination Mode */ 143 uint32_t fault_disable:1; /* Fault Processing Disable */ 144 uint32_t present:1; /* Whether entry present/available */ 145 #else 146 uint32_t present:1; /* Whether entry present/available */ 147 uint32_t fault_disable:1; /* Fault Processing Disable */ 148 uint32_t dest_mode:1; /* Destination Mode */ 149 uint32_t redir_hint:1; /* Redirection Hint */ 150 uint32_t trigger_mode:1; /* Trigger Mode */ 151 uint32_t delivery_mode:3; /* Delivery Mode */ 152 uint32_t __avail:4; /* Available spaces for software */ 153 uint32_t __reserved_0:3; /* Reserved 0 */ 154 uint32_t irte_mode:1; /* IRTE Mode */ 155 uint32_t vector:8; /* Interrupt Vector */ 156 uint32_t __reserved_1:8; /* Reserved 1 */ 157 #endif 158 uint32_t dest_id; /* Destination ID */ 159 uint16_t source_id; /* Source-ID */ 160 #ifdef HOST_WORDS_BIGENDIAN 161 uint64_t __reserved_2:44; /* Reserved 2 */ 162 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 163 uint64_t sid_q:2; /* Source-ID Qualifier */ 164 #else 165 uint64_t sid_q:2; /* Source-ID Qualifier */ 166 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 167 uint64_t __reserved_2:44; /* Reserved 2 */ 168 #endif 169 } QEMU_PACKED irte; 170 uint64_t data[2]; 171 }; 172 173 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */ 174 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */ 175 176 /* Programming format for MSI/MSI-X addresses */ 177 union VTD_IR_MSIAddress { 178 struct { 179 #ifdef HOST_WORDS_BIGENDIAN 180 uint32_t __head:12; /* Should always be: 0x0fee */ 181 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 182 uint32_t int_mode:1; /* Interrupt format */ 183 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 184 uint32_t index_h:1; /* Interrupt index bit 15 */ 185 uint32_t __not_care:2; 186 #else 187 uint32_t __not_care:2; 188 uint32_t index_h:1; /* Interrupt index bit 15 */ 189 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 190 uint32_t int_mode:1; /* Interrupt format */ 191 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 192 uint32_t __head:12; /* Should always be: 0x0fee */ 193 #endif 194 } QEMU_PACKED addr; 195 uint32_t data; 196 }; 197 198 /* When IR is enabled, all MSI/MSI-X data bits should be zero */ 199 #define VTD_IR_MSI_DATA (0) 200 201 /* The iommu (DMAR) device state struct */ 202 struct IntelIOMMUState { 203 X86IOMMUState x86_iommu; 204 MemoryRegion csrmem; 205 uint8_t csr[DMAR_REG_SIZE]; /* register values */ 206 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ 207 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ 208 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ 209 uint32_t version; 210 211 bool caching_mode; /* RO - is cap CM enabled? */ 212 213 dma_addr_t root; /* Current root table pointer */ 214 bool root_extended; /* Type of root table (extended or not) */ 215 bool dmar_enabled; /* Set if DMA remapping is enabled */ 216 217 uint16_t iq_head; /* Current invalidation queue head */ 218 uint16_t iq_tail; /* Current invalidation queue tail */ 219 dma_addr_t iq; /* Current invalidation queue pointer */ 220 uint16_t iq_size; /* IQ Size in number of entries */ 221 bool qi_enabled; /* Set if the QI is enabled */ 222 uint8_t iq_last_desc_type; /* The type of last completed descriptor */ 223 224 /* The index of the Fault Recording Register to be used next. 225 * Wraps around from N-1 to 0, where N is the number of FRCD_REG. 226 */ 227 uint16_t next_frcd_reg; 228 229 uint64_t cap; /* The value of capability reg */ 230 uint64_t ecap; /* The value of extended capability reg */ 231 232 uint32_t context_cache_gen; /* Should be in [1,MAX] */ 233 GHashTable *iotlb; /* IOTLB */ 234 235 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */ 236 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */ 237 /* list of registered notifiers */ 238 QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; 239 240 /* interrupt remapping */ 241 bool intr_enabled; /* Whether guest enabled IR */ 242 dma_addr_t intr_root; /* Interrupt remapping table pointer */ 243 uint32_t intr_size; /* Number of IR table entries */ 244 bool intr_eime; /* Extended interrupt mode enabled */ 245 OnOffAuto intr_eim; /* Toggle for EIM cabability */ 246 bool buggy_eim; /* Force buggy EIM unless eim=off */ 247 uint8_t aw_bits; /* Host/IOVA address width (in bits) */ 248 bool dma_drain; /* Whether DMA r/w draining enabled */ 249 250 /* 251 * Protects IOMMU states in general. Currently it protects the 252 * per-IOMMU IOTLB cache, and context entry cache in VTDAddressSpace. 253 */ 254 QemuMutex iommu_lock; 255 }; 256 257 /* Find the VTD Address space associated with the given bus pointer, 258 * create a new one if none exists 259 */ 260 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn); 261 262 #endif 263