1 /* 2 * QEMU emulation of an Intel IOMMU (VT-d) 3 * (DMA Remapping device) 4 * 5 * Copyright (C) 2013 Knut Omang, Oracle <knut.omang@oracle.com> 6 * Copyright (C) 2014 Le Tan, <tamlokveer@gmail.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #ifndef INTEL_IOMMU_H 23 #define INTEL_IOMMU_H 24 #include "hw/qdev.h" 25 #include "sysemu/dma.h" 26 #include "hw/i386/x86-iommu.h" 27 #include "hw/i386/ioapic.h" 28 #include "hw/pci/msi.h" 29 #include "hw/sysbus.h" 30 31 #define TYPE_INTEL_IOMMU_DEVICE "intel-iommu" 32 #define INTEL_IOMMU_DEVICE(obj) \ 33 OBJECT_CHECK(IntelIOMMUState, (obj), TYPE_INTEL_IOMMU_DEVICE) 34 35 #define TYPE_INTEL_IOMMU_MEMORY_REGION "intel-iommu-iommu-memory-region" 36 37 /* DMAR Hardware Unit Definition address (IOMMU unit) */ 38 #define Q35_HOST_BRIDGE_IOMMU_ADDR 0xfed90000ULL 39 40 #define VTD_PCI_BUS_MAX 256 41 #define VTD_PCI_SLOT_MAX 32 42 #define VTD_PCI_FUNC_MAX 8 43 #define VTD_PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f) 44 #define VTD_PCI_FUNC(devfn) ((devfn) & 0x07) 45 #define VTD_SID_TO_BUS(sid) (((sid) >> 8) & 0xff) 46 #define VTD_SID_TO_DEVFN(sid) ((sid) & 0xff) 47 48 #define DMAR_REG_SIZE 0x230 49 #define VTD_HOST_AW_39BIT 39 50 #define VTD_HOST_AW_48BIT 48 51 #define VTD_HOST_ADDRESS_WIDTH VTD_HOST_AW_39BIT 52 #define VTD_HAW_MASK(aw) ((1ULL << (aw)) - 1) 53 54 #define DMAR_REPORT_F_INTR (1) 55 56 #define VTD_MSI_ADDR_HI_MASK (0xffffffff00000000ULL) 57 #define VTD_MSI_ADDR_HI_SHIFT (32) 58 #define VTD_MSI_ADDR_LO_MASK (0x00000000ffffffffULL) 59 60 typedef struct VTDContextEntry VTDContextEntry; 61 typedef struct VTDContextCacheEntry VTDContextCacheEntry; 62 typedef struct IntelIOMMUState IntelIOMMUState; 63 typedef struct VTDAddressSpace VTDAddressSpace; 64 typedef struct VTDIOTLBEntry VTDIOTLBEntry; 65 typedef struct VTDBus VTDBus; 66 typedef union VTD_IR_TableEntry VTD_IR_TableEntry; 67 typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; 68 typedef struct VTDIrq VTDIrq; 69 typedef struct VTD_MSIMessage VTD_MSIMessage; 70 typedef struct IntelIOMMUNotifierNode IntelIOMMUNotifierNode; 71 72 /* Context-Entry */ 73 struct VTDContextEntry { 74 uint64_t lo; 75 uint64_t hi; 76 }; 77 78 struct VTDContextCacheEntry { 79 /* The cache entry is obsolete if 80 * context_cache_gen!=IntelIOMMUState.context_cache_gen 81 */ 82 uint32_t context_cache_gen; 83 struct VTDContextEntry context_entry; 84 }; 85 86 struct VTDAddressSpace { 87 PCIBus *bus; 88 uint8_t devfn; 89 AddressSpace as; 90 IOMMUMemoryRegion iommu; 91 MemoryRegion root; 92 MemoryRegion sys_alias; 93 MemoryRegion iommu_ir; /* Interrupt region: 0xfeeXXXXX */ 94 IntelIOMMUState *iommu_state; 95 VTDContextCacheEntry context_cache_entry; 96 }; 97 98 struct VTDBus { 99 PCIBus* bus; /* A reference to the bus to provide translation for */ 100 VTDAddressSpace *dev_as[0]; /* A table of VTDAddressSpace objects indexed by devfn */ 101 }; 102 103 struct VTDIOTLBEntry { 104 uint64_t gfn; 105 uint16_t domain_id; 106 uint64_t slpte; 107 uint64_t mask; 108 uint8_t access_flags; 109 }; 110 111 /* VT-d Source-ID Qualifier types */ 112 enum { 113 VTD_SQ_FULL = 0x00, /* Full SID verification */ 114 VTD_SQ_IGN_3 = 0x01, /* Ignore bit 3 */ 115 VTD_SQ_IGN_2_3 = 0x02, /* Ignore bits 2 & 3 */ 116 VTD_SQ_IGN_1_3 = 0x03, /* Ignore bits 1-3 */ 117 VTD_SQ_MAX, 118 }; 119 120 /* VT-d Source Validation Types */ 121 enum { 122 VTD_SVT_NONE = 0x00, /* No validation */ 123 VTD_SVT_ALL = 0x01, /* Do full validation */ 124 VTD_SVT_BUS = 0x02, /* Validate bus range */ 125 VTD_SVT_MAX, 126 }; 127 128 /* Interrupt Remapping Table Entry Definition */ 129 union VTD_IR_TableEntry { 130 struct { 131 #ifdef HOST_WORDS_BIGENDIAN 132 uint32_t __reserved_1:8; /* Reserved 1 */ 133 uint32_t vector:8; /* Interrupt Vector */ 134 uint32_t irte_mode:1; /* IRTE Mode */ 135 uint32_t __reserved_0:3; /* Reserved 0 */ 136 uint32_t __avail:4; /* Available spaces for software */ 137 uint32_t delivery_mode:3; /* Delivery Mode */ 138 uint32_t trigger_mode:1; /* Trigger Mode */ 139 uint32_t redir_hint:1; /* Redirection Hint */ 140 uint32_t dest_mode:1; /* Destination Mode */ 141 uint32_t fault_disable:1; /* Fault Processing Disable */ 142 uint32_t present:1; /* Whether entry present/available */ 143 #else 144 uint32_t present:1; /* Whether entry present/available */ 145 uint32_t fault_disable:1; /* Fault Processing Disable */ 146 uint32_t dest_mode:1; /* Destination Mode */ 147 uint32_t redir_hint:1; /* Redirection Hint */ 148 uint32_t trigger_mode:1; /* Trigger Mode */ 149 uint32_t delivery_mode:3; /* Delivery Mode */ 150 uint32_t __avail:4; /* Available spaces for software */ 151 uint32_t __reserved_0:3; /* Reserved 0 */ 152 uint32_t irte_mode:1; /* IRTE Mode */ 153 uint32_t vector:8; /* Interrupt Vector */ 154 uint32_t __reserved_1:8; /* Reserved 1 */ 155 #endif 156 uint32_t dest_id; /* Destination ID */ 157 uint16_t source_id; /* Source-ID */ 158 #ifdef HOST_WORDS_BIGENDIAN 159 uint64_t __reserved_2:44; /* Reserved 2 */ 160 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 161 uint64_t sid_q:2; /* Source-ID Qualifier */ 162 #else 163 uint64_t sid_q:2; /* Source-ID Qualifier */ 164 uint64_t sid_vtype:2; /* Source-ID Validation Type */ 165 uint64_t __reserved_2:44; /* Reserved 2 */ 166 #endif 167 } QEMU_PACKED irte; 168 uint64_t data[2]; 169 }; 170 171 #define VTD_IR_INT_FORMAT_COMPAT (0) /* Compatible Interrupt */ 172 #define VTD_IR_INT_FORMAT_REMAP (1) /* Remappable Interrupt */ 173 174 /* Programming format for MSI/MSI-X addresses */ 175 union VTD_IR_MSIAddress { 176 struct { 177 #ifdef HOST_WORDS_BIGENDIAN 178 uint32_t __head:12; /* Should always be: 0x0fee */ 179 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 180 uint32_t int_mode:1; /* Interrupt format */ 181 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 182 uint32_t index_h:1; /* Interrupt index bit 15 */ 183 uint32_t __not_care:2; 184 #else 185 uint32_t __not_care:2; 186 uint32_t index_h:1; /* Interrupt index bit 15 */ 187 uint32_t sub_valid:1; /* SHV: Sub-Handle Valid bit */ 188 uint32_t int_mode:1; /* Interrupt format */ 189 uint32_t index_l:15; /* Interrupt index bit 14-0 */ 190 uint32_t __head:12; /* Should always be: 0x0fee */ 191 #endif 192 } QEMU_PACKED addr; 193 uint32_t data; 194 }; 195 196 /* Generic IRQ entry information */ 197 struct VTDIrq { 198 /* Used by both IOAPIC/MSI interrupt remapping */ 199 uint8_t trigger_mode; 200 uint8_t vector; 201 uint8_t delivery_mode; 202 uint32_t dest; 203 uint8_t dest_mode; 204 205 /* only used by MSI interrupt remapping */ 206 uint8_t redir_hint; 207 uint8_t msi_addr_last_bits; 208 }; 209 210 struct VTD_MSIMessage { 211 union { 212 struct { 213 #ifdef HOST_WORDS_BIGENDIAN 214 uint32_t __addr_head:12; /* 0xfee */ 215 uint32_t dest:8; 216 uint32_t __reserved:8; 217 uint32_t redir_hint:1; 218 uint32_t dest_mode:1; 219 uint32_t __not_used:2; 220 #else 221 uint32_t __not_used:2; 222 uint32_t dest_mode:1; 223 uint32_t redir_hint:1; 224 uint32_t __reserved:8; 225 uint32_t dest:8; 226 uint32_t __addr_head:12; /* 0xfee */ 227 #endif 228 uint32_t __addr_hi; 229 } QEMU_PACKED; 230 uint64_t msi_addr; 231 }; 232 union { 233 struct { 234 #ifdef HOST_WORDS_BIGENDIAN 235 uint16_t trigger_mode:1; 236 uint16_t level:1; 237 uint16_t __resved:3; 238 uint16_t delivery_mode:3; 239 uint16_t vector:8; 240 #else 241 uint16_t vector:8; 242 uint16_t delivery_mode:3; 243 uint16_t __resved:3; 244 uint16_t level:1; 245 uint16_t trigger_mode:1; 246 #endif 247 uint16_t __resved1; 248 } QEMU_PACKED; 249 uint32_t msi_data; 250 }; 251 }; 252 253 /* When IR is enabled, all MSI/MSI-X data bits should be zero */ 254 #define VTD_IR_MSI_DATA (0) 255 256 struct IntelIOMMUNotifierNode { 257 VTDAddressSpace *vtd_as; 258 QLIST_ENTRY(IntelIOMMUNotifierNode) next; 259 }; 260 261 /* The iommu (DMAR) device state struct */ 262 struct IntelIOMMUState { 263 X86IOMMUState x86_iommu; 264 MemoryRegion csrmem; 265 uint8_t csr[DMAR_REG_SIZE]; /* register values */ 266 uint8_t wmask[DMAR_REG_SIZE]; /* R/W bytes */ 267 uint8_t w1cmask[DMAR_REG_SIZE]; /* RW1C(Write 1 to Clear) bytes */ 268 uint8_t womask[DMAR_REG_SIZE]; /* WO (write only - read returns 0) */ 269 uint32_t version; 270 271 bool caching_mode; /* RO - is cap CM enabled? */ 272 273 dma_addr_t root; /* Current root table pointer */ 274 bool root_extended; /* Type of root table (extended or not) */ 275 bool dmar_enabled; /* Set if DMA remapping is enabled */ 276 277 uint16_t iq_head; /* Current invalidation queue head */ 278 uint16_t iq_tail; /* Current invalidation queue tail */ 279 dma_addr_t iq; /* Current invalidation queue pointer */ 280 uint16_t iq_size; /* IQ Size in number of entries */ 281 bool qi_enabled; /* Set if the QI is enabled */ 282 uint8_t iq_last_desc_type; /* The type of last completed descriptor */ 283 284 /* The index of the Fault Recording Register to be used next. 285 * Wraps around from N-1 to 0, where N is the number of FRCD_REG. 286 */ 287 uint16_t next_frcd_reg; 288 289 uint64_t cap; /* The value of capability reg */ 290 uint64_t ecap; /* The value of extended capability reg */ 291 292 uint32_t context_cache_gen; /* Should be in [1,MAX] */ 293 GHashTable *iotlb; /* IOTLB */ 294 295 GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* reference */ 296 VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed by bus number */ 297 /* list of registered notifiers */ 298 QLIST_HEAD(, IntelIOMMUNotifierNode) notifiers_list; 299 300 /* interrupt remapping */ 301 bool intr_enabled; /* Whether guest enabled IR */ 302 dma_addr_t intr_root; /* Interrupt remapping table pointer */ 303 uint32_t intr_size; /* Number of IR table entries */ 304 bool intr_eime; /* Extended interrupt mode enabled */ 305 OnOffAuto intr_eim; /* Toggle for EIM cabability */ 306 bool buggy_eim; /* Force buggy EIM unless eim=off */ 307 uint8_t aw_bits; /* Host/IOVA address width (in bits) */ 308 }; 309 310 /* Find the VTD Address space associated with the given bus pointer, 311 * create a new one if none exists 312 */ 313 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn); 314 315 #endif 316