xref: /openbmc/qemu/include/hw/i2c/imx_i2c.h (revision a68694cd)
1 /*
2  *  i.MX I2C Bus Serial Interface registers definition
3  *
4  *  Copyright (C) 2013 Jean-Christophe Dubois. <jcd@tribudubois.net>
5  *
6  *  This program is free software; you can redistribute it and/or modify it
7  *  under the terms of the GNU General Public License as published by the
8  *  Free Software Foundation; either version 2 of the License, or
9  *  (at your option) any later version.
10  *
11  *  This program is distributed in the hope that it will be useful, but WITHOUT
12  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14  *  for more details.
15  *
16  *  You should have received a copy of the GNU General Public License along
17  *  with this program; if not, see <http://www.gnu.org/licenses/>.
18  *
19  */
20 
21 #ifndef IMX_I2C_H
22 #define IMX_I2C_H
23 
24 #include "hw/sysbus.h"
25 #include "qom/object.h"
26 
27 #define TYPE_IMX_I2C "imx.i2c"
28 typedef struct IMXI2CState IMXI2CState;
29 DECLARE_INSTANCE_CHECKER(IMXI2CState, IMX_I2C,
30                          TYPE_IMX_I2C)
31 
32 #define IMX_I2C_MEM_SIZE           0x14
33 
34 /* i.MX I2C memory map */
35 #define IADR_ADDR                  0x00  /* address register */
36 #define IFDR_ADDR                  0x04  /* frequency divider register */
37 #define I2CR_ADDR                  0x08  /* control register */
38 #define I2SR_ADDR                  0x0c  /* status register */
39 #define I2DR_ADDR                  0x10  /* data register */
40 
41 #define IADR_MASK                  0xFE
42 #define IADR_RESET                 0
43 
44 #define IFDR_MASK                  0x3F
45 #define IFDR_RESET                 0
46 
47 #define I2CR_IEN                   (1 << 7)
48 #define I2CR_IIEN                  (1 << 6)
49 #define I2CR_MSTA                  (1 << 5)
50 #define I2CR_MTX                   (1 << 4)
51 #define I2CR_TXAK                  (1 << 3)
52 #define I2CR_RSTA                  (1 << 2)
53 #define I2CR_MASK                  0xFC
54 #define I2CR_RESET                 0
55 
56 #define I2SR_ICF                   (1 << 7)
57 #define I2SR_IAAF                  (1 << 6)
58 #define I2SR_IBB                   (1 << 5)
59 #define I2SR_IAL                   (1 << 4)
60 #define I2SR_SRW                   (1 << 2)
61 #define I2SR_IIF                   (1 << 1)
62 #define I2SR_RXAK                  (1 << 0)
63 #define I2SR_MASK                  0xE9
64 #define I2SR_RESET                 0x81
65 
66 #define I2DR_MASK                  0xFF
67 #define I2DR_RESET                 0
68 
69 #define ADDR_RESET                 0xFF00
70 
71 struct IMXI2CState {
72     /*< private >*/
73     SysBusDevice parent_obj;
74 
75     /*< public >*/
76     MemoryRegion iomem;
77     I2CBus *bus;
78     qemu_irq irq;
79 
80     uint16_t  address;
81 
82     uint16_t iadr;
83     uint16_t ifdr;
84     uint16_t i2cr;
85     uint16_t i2sr;
86     uint16_t i2dr_read;
87     uint16_t i2dr_write;
88 };
89 
90 #endif /* IMX_I2C_H */
91