1 /* 2 * ASPEED AST2400 I2C Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #ifndef ASPEED_I2C_H 22 #define ASPEED_I2C_H 23 24 #include "hw/i2c/i2c.h" 25 #include "hw/sysbus.h" 26 #include "hw/registerfields.h" 27 #include "qom/object.h" 28 29 #define TYPE_ASPEED_I2C "aspeed.i2c" 30 #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" 31 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" 32 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" 33 OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) 34 35 #define ASPEED_I2C_NR_BUSSES 16 36 #define ASPEED_I2C_MAX_POOL_SIZE 0x800 37 #define ASPEED_I2C_OLD_NUM_REG 11 38 #define ASPEED_I2C_NEW_NUM_REG 22 39 40 /* Tx State Machine */ 41 #define I2CD_TX_STATE_MASK 0xf 42 #define I2CD_IDLE 0x0 43 #define I2CD_MACTIVE 0x8 44 #define I2CD_MSTART 0x9 45 #define I2CD_MSTARTR 0xa 46 #define I2CD_MSTOP 0xb 47 #define I2CD_MTXD 0xc 48 #define I2CD_MRXACK 0xd 49 #define I2CD_MRXD 0xe 50 #define I2CD_MTXACK 0xf 51 #define I2CD_SWAIT 0x1 52 #define I2CD_SRXD 0x4 53 #define I2CD_STXACK 0x5 54 #define I2CD_STXD 0x6 55 #define I2CD_SRXACK 0x7 56 #define I2CD_RECOVER 0x3 57 58 /* I2C Global Register */ 59 REG32(I2C_CTRL_STATUS, 0x0) /* Device Interrupt Status */ 60 REG32(I2C_CTRL_ASSIGN, 0x8) /* Device Interrupt Target Assignment */ 61 REG32(I2C_CTRL_GLOBAL, 0xC) /* Global Control Register */ 62 FIELD(I2C_CTRL_GLOBAL, REG_MODE, 2, 1) 63 FIELD(I2C_CTRL_GLOBAL, SRAM_EN, 0, 1) 64 REG32(I2C_CTRL_NEW_CLK_DIVIDER, 0x10) /* New mode clock divider */ 65 66 /* I2C Old Mode Device (Bus) Register */ 67 REG32(I2CD_FUN_CTRL, 0x0) /* I2CD Function Control */ 68 FIELD(I2CD_FUN_CTRL, POOL_PAGE_SEL, 20, 3) /* AST2400 */ 69 SHARED_FIELD(M_SDA_LOCK_EN, 16, 1) 70 SHARED_FIELD(MULTI_MASTER_DIS, 15, 1) 71 SHARED_FIELD(M_SCL_DRIVE_EN, 14, 1) 72 SHARED_FIELD(MSB_STS, 9, 1) 73 SHARED_FIELD(SDA_DRIVE_IT_EN, 8, 1) 74 SHARED_FIELD(M_SDA_DRIVE_IT_EN, 7, 1) 75 SHARED_FIELD(M_HIGH_SPEED_EN, 6, 1) 76 SHARED_FIELD(DEF_ADDR_EN, 5, 1) 77 SHARED_FIELD(DEF_ALERT_EN, 4, 1) 78 SHARED_FIELD(DEF_ARP_EN, 3, 1) 79 SHARED_FIELD(DEF_GCALL_EN, 2, 1) 80 SHARED_FIELD(SLAVE_EN, 1, 1) 81 SHARED_FIELD(MASTER_EN, 0, 1) 82 REG32(I2CD_AC_TIMING1, 0x04) /* Clock and AC Timing Control #1 */ 83 REG32(I2CD_AC_TIMING2, 0x08) /* Clock and AC Timing Control #2 */ 84 REG32(I2CD_INTR_CTRL, 0x0C) /* I2CD Interrupt Control */ 85 REG32(I2CD_INTR_STS, 0x10) /* I2CD Interrupt Status */ 86 SHARED_FIELD(SLAVE_ADDR_MATCH, 31, 1) /* 0: addr1 1: addr2 */ 87 SHARED_FIELD(SLAVE_ADDR_RX_PENDING, 29, 1) 88 SHARED_FIELD(SLAVE_INACTIVE_TIMEOUT, 15, 1) 89 SHARED_FIELD(SDA_DL_TIMEOUT, 14, 1) 90 SHARED_FIELD(BUS_RECOVER_DONE, 13, 1) 91 SHARED_FIELD(SMBUS_ALERT, 12, 1) /* Bus [0-3] only */ 92 FIELD(I2CD_INTR_STS, SMBUS_ARP_ADDR, 11, 1) /* Removed */ 93 FIELD(I2CD_INTR_STS, SMBUS_DEV_ALERT_ADDR, 10, 1) /* Removed */ 94 FIELD(I2CD_INTR_STS, SMBUS_DEF_ADDR, 9, 1) /* Removed */ 95 FIELD(I2CD_INTR_STS, GCALL_ADDR, 8, 1) /* Removed */ 96 FIELD(I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) /* use RX_DONE */ 97 SHARED_FIELD(SCL_TIMEOUT, 6, 1) 98 SHARED_FIELD(ABNORMAL, 5, 1) 99 SHARED_FIELD(NORMAL_STOP, 4, 1) 100 SHARED_FIELD(ARBIT_LOSS, 3, 1) 101 SHARED_FIELD(RX_DONE, 2, 1) 102 SHARED_FIELD(TX_NAK, 1, 1) 103 SHARED_FIELD(TX_ACK, 0, 1) 104 REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */ 105 SHARED_FIELD(SDA_OE, 28, 1) 106 SHARED_FIELD(SDA_O, 27, 1) 107 SHARED_FIELD(SCL_OE, 26, 1) 108 SHARED_FIELD(SCL_O, 25, 1) 109 SHARED_FIELD(TX_TIMING, 23, 2) 110 SHARED_FIELD(TX_STATE, 19, 4) 111 SHARED_FIELD(SCL_LINE_STS, 18, 1) 112 SHARED_FIELD(SDA_LINE_STS, 17, 1) 113 SHARED_FIELD(BUS_BUSY_STS, 16, 1) 114 SHARED_FIELD(SDA_OE_OUT_DIR, 15, 1) 115 SHARED_FIELD(SDA_O_OUT_DIR, 14, 1) 116 SHARED_FIELD(SCL_OE_OUT_DIR, 13, 1) 117 SHARED_FIELD(SCL_O_OUT_DIR, 12, 1) 118 SHARED_FIELD(BUS_RECOVER_CMD_EN, 11, 1) 119 SHARED_FIELD(S_ALT_EN, 10, 1) 120 /* Command Bits */ 121 SHARED_FIELD(RX_DMA_EN, 9, 1) 122 SHARED_FIELD(TX_DMA_EN, 8, 1) 123 SHARED_FIELD(RX_BUFF_EN, 7, 1) 124 SHARED_FIELD(TX_BUFF_EN, 6, 1) 125 SHARED_FIELD(M_STOP_CMD, 5, 1) 126 SHARED_FIELD(M_S_RX_CMD_LAST, 4, 1) 127 SHARED_FIELD(M_RX_CMD, 3, 1) 128 SHARED_FIELD(S_TX_CMD, 2, 1) 129 SHARED_FIELD(M_TX_CMD, 1, 1) 130 SHARED_FIELD(M_START_CMD, 0, 1) 131 REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */ 132 REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */ 133 SHARED_FIELD(RX_COUNT, 24, 5) 134 SHARED_FIELD(RX_SIZE, 16, 5) 135 SHARED_FIELD(TX_COUNT, 9, 5) 136 FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */ 137 REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */ 138 SHARED_FIELD(RX_BUF, 8, 8) 139 SHARED_FIELD(TX_BUF, 0, 8) 140 REG32(I2CD_DMA_ADDR, 0x24) /* DMA Buffer Address */ 141 REG32(I2CD_DMA_LEN, 0x28) /* DMA Transfer Length < 4KB */ 142 143 /* I2C New Mode Device (Bus) Register */ 144 REG32(I2CC_FUN_CTRL, 0x0) 145 FIELD(I2CC_FUN_CTRL, RB_EARLY_DONE_EN, 22, 1) 146 FIELD(I2CC_FUN_CTRL, DMA_DIS_AUTO_RECOVER, 21, 1) 147 FIELD(I2CC_FUN_CTRL, S_SAVE_ADDR, 20, 1) 148 FIELD(I2CC_FUN_CTRL, M_PKT_RETRY_CNT, 18, 2) 149 /* 17:0 shared with I2CD_FUN_CTRL[17:0] */ 150 REG32(I2CC_AC_TIMING, 0x04) 151 REG32(I2CC_MS_TXRX_BYTE_BUF, 0x08) 152 /* 31:16 shared with I2CD_CMD[31:16] */ 153 /* 15:0 shared with I2CD_BYTE_BUF[15:0] */ 154 REG32(I2CC_POOL_CTRL, 0x0c) 155 /* 31:0 shared with I2CD_POOL_CTRL[31:0] */ 156 REG32(I2CM_INTR_CTRL, 0x10) 157 REG32(I2CM_INTR_STS, 0x14) 158 FIELD(I2CM_INTR_STS, PKT_STATE, 28, 4) 159 FIELD(I2CM_INTR_STS, PKT_CMD_TIMEOUT, 18, 1) 160 FIELD(I2CM_INTR_STS, PKT_CMD_FAIL, 17, 1) 161 FIELD(I2CM_INTR_STS, PKT_CMD_DONE, 16, 1) 162 FIELD(I2CM_INTR_STS, BUS_RECOVER_FAIL, 15, 1) 163 /* 14:0 shared with I2CD_INTR_STS[14:0] */ 164 REG32(I2CM_CMD, 0x18) 165 FIELD(I2CM_CMD, W1_CTRL, 31, 1) 166 FIELD(I2CM_CMD, PKT_DEV_ADDR, 24, 7) 167 FIELD(I2CM_CMD, HS_MASTER_MODE_LSB, 17, 3) 168 FIELD(I2CM_CMD, PKT_OP_EN, 16, 1) 169 /* 15:0 shared with I2CD_CMD[15:0] */ 170 REG32(I2CM_DMA_LEN, 0x1c) 171 FIELD(I2CM_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) 172 FIELD(I2CM_DMA_LEN, RX_BUF_LEN, 16, 11) 173 FIELD(I2CM_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) 174 FIELD(I2CM_DMA_LEN, TX_BUF_LEN, 0, 11) 175 REG32(I2CS_INTR_CTRL, 0x20) 176 REG32(I2CS_INTR_STS, 0x24) 177 /* 31:29 shared with I2CD_INTR_STS[31:29] */ 178 FIELD(I2CS_INTR_STS, SLAVE_PARKING_STS, 24, 2) 179 FIELD(I2CS_INTR_STS, SLAVE_ADDR3_NAK, 22, 1) 180 FIELD(I2CS_INTR_STS, SLAVE_ADDR2_NAK, 21, 1) 181 FIELD(I2CS_INTR_STS, SLAVE_ADDR1_NAK, 20, 1) 182 FIELD(I2CS_INTR_STS, SLAVE_ADDR_INDICATOR, 18, 2) 183 FIELD(I2CS_INTR_STS, PKT_CMD_FAIL, 17, 1) 184 FIELD(I2CS_INTR_STS, PKT_CMD_DONE, 16, 1) 185 /* 14:0 shared with I2CD_INTR_STS[14:0] */ 186 REG32(I2CS_CMD, 0x28) 187 FIELD(I2CS_CMD, W1_CTRL, 31, 1) 188 FIELD(I2CS_CMD, PKT_MODE_ACTIVE_ADDR, 17, 2) 189 FIELD(I2CS_CMD, PKT_MODE_EN, 16, 1) 190 FIELD(I2CS_CMD, AUTO_NAK_INACTIVE_ADDR, 15, 1) 191 FIELD(I2CS_CMD, AUTO_NAK_ACTIVE_ADDR, 14, 1) 192 /* 13:0 shared with I2CD_CMD[13:0] */ 193 REG32(I2CS_DMA_LEN, 0x2c) 194 FIELD(I2CS_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) 195 FIELD(I2CS_DMA_LEN, RX_BUF_LEN, 16, 11) 196 FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) 197 FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11) 198 REG32(I2CM_DMA_TX_ADDR, 0x30) 199 FIELD(I2CM_DMA_TX_ADDR, ADDR, 0, 31) 200 REG32(I2CM_DMA_RX_ADDR, 0x34) 201 FIELD(I2CM_DMA_RX_ADDR, ADDR, 0, 31) 202 REG32(I2CS_DMA_TX_ADDR, 0x38) 203 FIELD(I2CS_DMA_TX_ADDR, ADDR, 0, 31) 204 REG32(I2CS_DMA_RX_ADDR, 0x3c) 205 FIELD(I2CS_DMA_RX_ADDR, ADDR, 0, 31) 206 REG32(I2CS_DEV_ADDR, 0x40) 207 REG32(I2CM_DMA_LEN_STS, 0x48) 208 FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13) 209 FIELD(I2CM_DMA_LEN_STS, TX_LEN, 0, 13) 210 REG32(I2CS_DMA_LEN_STS, 0x4c) 211 FIELD(I2CS_DMA_LEN_STS, RX_LEN, 16, 13) 212 FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13) 213 REG32(I2CC_DMA_ADDR, 0x50) 214 REG32(I2CC_DMA_LEN, 0x54) 215 216 struct AspeedI2CState; 217 218 #define TYPE_ASPEED_I2C_BUS "aspeed.i2c.bus" 219 OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBus, ASPEED_I2C_BUS) 220 struct AspeedI2CBus { 221 SysBusDevice parent_obj; 222 223 struct AspeedI2CState *controller; 224 225 MemoryRegion mr; 226 227 I2CBus *bus; 228 uint8_t id; 229 qemu_irq irq; 230 231 uint32_t regs[ASPEED_I2C_NEW_NUM_REG]; 232 }; 233 234 struct AspeedI2CState { 235 SysBusDevice parent_obj; 236 237 MemoryRegion iomem; 238 qemu_irq irq; 239 240 uint32_t intr_status; 241 uint32_t ctrl_global; 242 uint32_t new_clk_divider; 243 MemoryRegion pool_iomem; 244 uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; 245 246 AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; 247 MemoryRegion *dram_mr; 248 AddressSpace dram_as; 249 }; 250 251 252 struct AspeedI2CClass { 253 SysBusDeviceClass parent_class; 254 255 uint8_t num_busses; 256 uint8_t reg_size; 257 uint8_t gap; 258 qemu_irq (*bus_get_irq)(AspeedI2CBus *); 259 260 uint64_t pool_size; 261 hwaddr pool_base; 262 uint8_t *(*bus_pool_base)(AspeedI2CBus *); 263 bool check_sram; 264 bool has_dma; 265 266 }; 267 268 static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s) 269 { 270 return FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, REG_MODE); 271 } 272 273 static inline bool aspeed_i2c_bus_pkt_mode_en(AspeedI2CBus *bus) 274 { 275 if (aspeed_i2c_is_new_mode(bus->controller)) { 276 return ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_OP_EN); 277 } 278 return false; 279 } 280 281 static inline uint32_t aspeed_i2c_bus_ctrl_offset(AspeedI2CBus *bus) 282 { 283 if (aspeed_i2c_is_new_mode(bus->controller)) { 284 return R_I2CC_FUN_CTRL; 285 } 286 return R_I2CD_FUN_CTRL; 287 } 288 289 static inline uint32_t aspeed_i2c_bus_cmd_offset(AspeedI2CBus *bus) 290 { 291 if (aspeed_i2c_is_new_mode(bus->controller)) { 292 return R_I2CM_CMD; 293 } 294 return R_I2CD_CMD; 295 } 296 297 static inline uint32_t aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus *bus) 298 { 299 if (aspeed_i2c_is_new_mode(bus->controller)) { 300 return R_I2CM_INTR_CTRL; 301 } 302 return R_I2CD_INTR_CTRL; 303 } 304 305 static inline uint32_t aspeed_i2c_bus_intr_sts_offset(AspeedI2CBus *bus) 306 { 307 if (aspeed_i2c_is_new_mode(bus->controller)) { 308 return R_I2CM_INTR_STS; 309 } 310 return R_I2CD_INTR_STS; 311 } 312 313 static inline uint32_t aspeed_i2c_bus_pool_ctrl_offset(AspeedI2CBus *bus) 314 { 315 if (aspeed_i2c_is_new_mode(bus->controller)) { 316 return R_I2CC_POOL_CTRL; 317 } 318 return R_I2CD_POOL_CTRL; 319 } 320 321 static inline uint32_t aspeed_i2c_bus_byte_buf_offset(AspeedI2CBus *bus) 322 { 323 if (aspeed_i2c_is_new_mode(bus->controller)) { 324 return R_I2CC_MS_TXRX_BYTE_BUF; 325 } 326 return R_I2CD_BYTE_BUF; 327 } 328 329 static inline uint32_t aspeed_i2c_bus_dma_len_offset(AspeedI2CBus *bus) 330 { 331 if (aspeed_i2c_is_new_mode(bus->controller)) { 332 return R_I2CC_DMA_LEN; 333 } 334 return R_I2CD_DMA_LEN; 335 } 336 337 static inline uint32_t aspeed_i2c_bus_dma_addr_offset(AspeedI2CBus *bus) 338 { 339 if (aspeed_i2c_is_new_mode(bus->controller)) { 340 return R_I2CC_DMA_ADDR; 341 } 342 return R_I2CD_DMA_ADDR; 343 } 344 345 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) 346 { 347 return SHARED_ARRAY_FIELD_EX32(bus->regs, aspeed_i2c_bus_ctrl_offset(bus), 348 MASTER_EN); 349 } 350 351 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) 352 { 353 uint32_t ctrl_reg = aspeed_i2c_bus_ctrl_offset(bus); 354 return SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, MASTER_EN) || 355 SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, SLAVE_EN); 356 } 357 358 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr); 359 360 #endif /* ASPEED_I2C_H */ 361