1 /* 2 * ASPEED AST2400 I2C Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #ifndef ASPEED_I2C_H 22 #define ASPEED_I2C_H 23 24 #include "hw/i2c/i2c.h" 25 #include "hw/sysbus.h" 26 #include "hw/registerfields.h" 27 #include "qom/object.h" 28 29 #define TYPE_ASPEED_I2C "aspeed.i2c" 30 #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" 31 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" 32 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" 33 #define TYPE_ASPEED_1030_I2C TYPE_ASPEED_I2C "-ast1030" 34 OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) 35 36 #define ASPEED_I2C_NR_BUSSES 16 37 #define ASPEED_I2C_MAX_POOL_SIZE 0x800 38 #define ASPEED_I2C_OLD_NUM_REG 11 39 #define ASPEED_I2C_NEW_NUM_REG 22 40 41 #define A_I2CD_M_STOP_CMD BIT(5) 42 #define A_I2CD_M_RX_CMD BIT(3) 43 #define A_I2CD_M_TX_CMD BIT(1) 44 #define A_I2CD_M_START_CMD BIT(0) 45 46 #define A_I2CD_MASTER_EN BIT(0) 47 48 /* Tx State Machine */ 49 #define I2CD_TX_STATE_MASK 0xf 50 #define I2CD_IDLE 0x0 51 #define I2CD_MACTIVE 0x8 52 #define I2CD_MSTART 0x9 53 #define I2CD_MSTARTR 0xa 54 #define I2CD_MSTOP 0xb 55 #define I2CD_MTXD 0xc 56 #define I2CD_MRXACK 0xd 57 #define I2CD_MRXD 0xe 58 #define I2CD_MTXACK 0xf 59 #define I2CD_SWAIT 0x1 60 #define I2CD_SRXD 0x4 61 #define I2CD_STXACK 0x5 62 #define I2CD_STXD 0x6 63 #define I2CD_SRXACK 0x7 64 #define I2CD_RECOVER 0x3 65 66 /* I2C Global Register */ 67 REG32(I2C_CTRL_STATUS, 0x0) /* Device Interrupt Status */ 68 REG32(I2C_CTRL_ASSIGN, 0x8) /* Device Interrupt Target Assignment */ 69 REG32(I2C_CTRL_GLOBAL, 0xC) /* Global Control Register */ 70 FIELD(I2C_CTRL_GLOBAL, REG_MODE, 2, 1) 71 FIELD(I2C_CTRL_GLOBAL, SRAM_EN, 0, 1) 72 REG32(I2C_CTRL_NEW_CLK_DIVIDER, 0x10) /* New mode clock divider */ 73 74 /* I2C Old Mode Device (Bus) Register */ 75 REG32(I2CD_FUN_CTRL, 0x0) /* I2CD Function Control */ 76 FIELD(I2CD_FUN_CTRL, POOL_PAGE_SEL, 20, 3) /* AST2400 */ 77 SHARED_FIELD(M_SDA_LOCK_EN, 16, 1) 78 SHARED_FIELD(MULTI_MASTER_DIS, 15, 1) 79 SHARED_FIELD(M_SCL_DRIVE_EN, 14, 1) 80 SHARED_FIELD(MSB_STS, 9, 1) 81 SHARED_FIELD(SDA_DRIVE_IT_EN, 8, 1) 82 SHARED_FIELD(M_SDA_DRIVE_IT_EN, 7, 1) 83 SHARED_FIELD(M_HIGH_SPEED_EN, 6, 1) 84 SHARED_FIELD(DEF_ADDR_EN, 5, 1) 85 SHARED_FIELD(DEF_ALERT_EN, 4, 1) 86 SHARED_FIELD(DEF_ARP_EN, 3, 1) 87 SHARED_FIELD(DEF_GCALL_EN, 2, 1) 88 SHARED_FIELD(SLAVE_EN, 1, 1) 89 SHARED_FIELD(MASTER_EN, 0, 1) 90 REG32(I2CD_AC_TIMING1, 0x04) /* Clock and AC Timing Control #1 */ 91 REG32(I2CD_AC_TIMING2, 0x08) /* Clock and AC Timing Control #2 */ 92 REG32(I2CD_INTR_CTRL, 0x0C) /* I2CD Interrupt Control */ 93 REG32(I2CD_INTR_STS, 0x10) /* I2CD Interrupt Status */ 94 SHARED_FIELD(SLAVE_ADDR_MATCH, 31, 1) /* 0: addr1 1: addr2 */ 95 SHARED_FIELD(SLAVE_ADDR_RX_PENDING, 29, 1) 96 SHARED_FIELD(SLAVE_INACTIVE_TIMEOUT, 15, 1) 97 SHARED_FIELD(SDA_DL_TIMEOUT, 14, 1) 98 SHARED_FIELD(BUS_RECOVER_DONE, 13, 1) 99 SHARED_FIELD(SMBUS_ALERT, 12, 1) /* Bus [0-3] only */ 100 FIELD(I2CD_INTR_STS, SMBUS_ARP_ADDR, 11, 1) /* Removed */ 101 FIELD(I2CD_INTR_STS, SMBUS_DEV_ALERT_ADDR, 10, 1) /* Removed */ 102 FIELD(I2CD_INTR_STS, SMBUS_DEF_ADDR, 9, 1) /* Removed */ 103 FIELD(I2CD_INTR_STS, GCALL_ADDR, 8, 1) /* Removed */ 104 FIELD(I2CD_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) /* use RX_DONE */ 105 SHARED_FIELD(SCL_TIMEOUT, 6, 1) 106 SHARED_FIELD(ABNORMAL, 5, 1) 107 SHARED_FIELD(NORMAL_STOP, 4, 1) 108 SHARED_FIELD(ARBIT_LOSS, 3, 1) 109 SHARED_FIELD(RX_DONE, 2, 1) 110 SHARED_FIELD(TX_NAK, 1, 1) 111 SHARED_FIELD(TX_ACK, 0, 1) 112 REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */ 113 SHARED_FIELD(SDA_OE, 28, 1) 114 SHARED_FIELD(SDA_O, 27, 1) 115 SHARED_FIELD(SCL_OE, 26, 1) 116 SHARED_FIELD(SCL_O, 25, 1) 117 SHARED_FIELD(TX_TIMING, 23, 2) 118 SHARED_FIELD(TX_STATE, 19, 4) 119 SHARED_FIELD(SCL_LINE_STS, 18, 1) 120 SHARED_FIELD(SDA_LINE_STS, 17, 1) 121 SHARED_FIELD(BUS_BUSY_STS, 16, 1) 122 SHARED_FIELD(SDA_OE_OUT_DIR, 15, 1) 123 SHARED_FIELD(SDA_O_OUT_DIR, 14, 1) 124 SHARED_FIELD(SCL_OE_OUT_DIR, 13, 1) 125 SHARED_FIELD(SCL_O_OUT_DIR, 12, 1) 126 SHARED_FIELD(BUS_RECOVER_CMD_EN, 11, 1) 127 SHARED_FIELD(S_ALT_EN, 10, 1) 128 /* Command Bits */ 129 SHARED_FIELD(RX_DMA_EN, 9, 1) 130 SHARED_FIELD(TX_DMA_EN, 8, 1) 131 SHARED_FIELD(RX_BUFF_EN, 7, 1) 132 SHARED_FIELD(TX_BUFF_EN, 6, 1) 133 SHARED_FIELD(M_STOP_CMD, 5, 1) 134 SHARED_FIELD(M_S_RX_CMD_LAST, 4, 1) 135 SHARED_FIELD(M_RX_CMD, 3, 1) 136 SHARED_FIELD(S_TX_CMD, 2, 1) 137 SHARED_FIELD(M_TX_CMD, 1, 1) 138 SHARED_FIELD(M_START_CMD, 0, 1) 139 REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */ 140 SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7) 141 REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */ 142 SHARED_FIELD(RX_COUNT, 24, 6) 143 SHARED_FIELD(RX_SIZE, 16, 5) 144 SHARED_FIELD(TX_COUNT, 8, 5) 145 FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */ 146 SHARED_FIELD(BUF_ORGANIZATION, 0, 1) /* AST2600 */ 147 REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */ 148 SHARED_FIELD(RX_BUF, 8, 8) 149 SHARED_FIELD(TX_BUF, 0, 8) 150 REG32(I2CD_DMA_ADDR, 0x24) /* DMA Buffer Address */ 151 REG32(I2CD_DMA_LEN, 0x28) /* DMA Transfer Length < 4KB */ 152 153 /* I2C New Mode Device (Bus) Register */ 154 REG32(I2CC_FUN_CTRL, 0x0) 155 FIELD(I2CC_FUN_CTRL, RB_EARLY_DONE_EN, 22, 1) 156 FIELD(I2CC_FUN_CTRL, DMA_DIS_AUTO_RECOVER, 21, 1) 157 FIELD(I2CC_FUN_CTRL, S_SAVE_ADDR, 20, 1) 158 FIELD(I2CC_FUN_CTRL, M_PKT_RETRY_CNT, 18, 2) 159 /* 17:0 shared with I2CD_FUN_CTRL[17:0] */ 160 REG32(I2CC_AC_TIMING, 0x04) 161 REG32(I2CC_MS_TXRX_BYTE_BUF, 0x08) 162 /* 31:16 shared with I2CD_CMD[31:16] */ 163 /* 15:0 shared with I2CD_BYTE_BUF[15:0] */ 164 REG32(I2CC_POOL_CTRL, 0x0c) 165 /* 31:0 shared with I2CD_POOL_CTRL[31:0] */ 166 REG32(I2CM_INTR_CTRL, 0x10) 167 REG32(I2CM_INTR_STS, 0x14) 168 FIELD(I2CM_INTR_STS, PKT_STATE, 28, 4) 169 FIELD(I2CM_INTR_STS, PKT_CMD_TIMEOUT, 18, 1) 170 FIELD(I2CM_INTR_STS, PKT_CMD_FAIL, 17, 1) 171 FIELD(I2CM_INTR_STS, PKT_CMD_DONE, 16, 1) 172 FIELD(I2CM_INTR_STS, BUS_RECOVER_FAIL, 15, 1) 173 /* 14:0 shared with I2CD_INTR_STS[14:0] */ 174 REG32(I2CM_CMD, 0x18) 175 FIELD(I2CM_CMD, W1_CTRL, 31, 1) 176 FIELD(I2CM_CMD, PKT_DEV_ADDR, 24, 7) 177 FIELD(I2CM_CMD, HS_MASTER_MODE_LSB, 17, 3) 178 FIELD(I2CM_CMD, PKT_OP_EN, 16, 1) 179 /* 15:0 shared with I2CD_CMD[15:0] */ 180 REG32(I2CM_DMA_LEN, 0x1c) 181 FIELD(I2CM_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) 182 FIELD(I2CM_DMA_LEN, RX_BUF_LEN, 16, 11) 183 FIELD(I2CM_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) 184 FIELD(I2CM_DMA_LEN, TX_BUF_LEN, 0, 11) 185 REG32(I2CS_INTR_CTRL, 0x20) 186 FIELD(I2CS_INTR_CTRL, PKT_CMD_FAIL, 17, 1) 187 FIELD(I2CS_INTR_CTRL, PKT_CMD_DONE, 16, 1) 188 REG32(I2CS_INTR_STS, 0x24) 189 /* 31:29 shared with I2CD_INTR_STS[31:29] */ 190 FIELD(I2CS_INTR_STS, SLAVE_PARKING_STS, 24, 2) 191 FIELD(I2CS_INTR_STS, SLAVE_ADDR3_NAK, 22, 1) 192 FIELD(I2CS_INTR_STS, SLAVE_ADDR2_NAK, 21, 1) 193 FIELD(I2CS_INTR_STS, SLAVE_ADDR1_NAK, 20, 1) 194 FIELD(I2CS_INTR_STS, SLAVE_ADDR_INDICATOR, 18, 2) 195 FIELD(I2CS_INTR_STS, PKT_CMD_FAIL, 17, 1) 196 FIELD(I2CS_INTR_STS, PKT_CMD_DONE, 16, 1) 197 /* 14:0 shared with I2CD_INTR_STS[14:0] */ 198 FIELD(I2CS_INTR_STS, SLAVE_ADDR_RX_MATCH, 7, 1) 199 REG32(I2CS_CMD, 0x28) 200 FIELD(I2CS_CMD, W1_CTRL, 31, 1) 201 FIELD(I2CS_CMD, PKT_MODE_ACTIVE_ADDR, 17, 2) 202 FIELD(I2CS_CMD, PKT_MODE_EN, 16, 1) 203 FIELD(I2CS_CMD, AUTO_NAK_INACTIVE_ADDR, 15, 1) 204 FIELD(I2CS_CMD, AUTO_NAK_ACTIVE_ADDR, 14, 1) 205 /* 13:0 shared with I2CD_CMD[13:0] */ 206 REG32(I2CS_DMA_LEN, 0x2c) 207 FIELD(I2CS_DMA_LEN, RX_BUF_LEN_W1T, 31, 1) 208 FIELD(I2CS_DMA_LEN, RX_BUF_LEN, 16, 11) 209 FIELD(I2CS_DMA_LEN, TX_BUF_LEN_W1T, 15, 1) 210 FIELD(I2CS_DMA_LEN, TX_BUF_LEN, 0, 11) 211 REG32(I2CM_DMA_TX_ADDR, 0x30) 212 FIELD(I2CM_DMA_TX_ADDR, ADDR, 0, 31) 213 REG32(I2CM_DMA_RX_ADDR, 0x34) 214 FIELD(I2CM_DMA_RX_ADDR, ADDR, 0, 31) 215 REG32(I2CS_DMA_TX_ADDR, 0x38) 216 FIELD(I2CS_DMA_TX_ADDR, ADDR, 0, 31) 217 REG32(I2CS_DMA_RX_ADDR, 0x3c) 218 FIELD(I2CS_DMA_RX_ADDR, ADDR, 0, 31) 219 REG32(I2CS_DEV_ADDR, 0x40) 220 REG32(I2CM_DMA_LEN_STS, 0x48) 221 FIELD(I2CM_DMA_LEN_STS, RX_LEN, 16, 13) 222 FIELD(I2CM_DMA_LEN_STS, TX_LEN, 0, 13) 223 REG32(I2CS_DMA_LEN_STS, 0x4c) 224 FIELD(I2CS_DMA_LEN_STS, RX_LEN, 16, 13) 225 FIELD(I2CS_DMA_LEN_STS, TX_LEN, 0, 13) 226 REG32(I2CC_DMA_ADDR, 0x50) 227 REG32(I2CC_DMA_LEN, 0x54) 228 229 struct AspeedI2CState; 230 231 #define TYPE_ASPEED_I2C_BUS "aspeed.i2c.bus" 232 OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBus, ASPEED_I2C_BUS) 233 struct AspeedI2CBus { 234 SysBusDevice parent_obj; 235 236 struct AspeedI2CState *controller; 237 238 /* slave mode */ 239 I2CSlave *slave; 240 241 MemoryRegion mr; 242 243 I2CBus *bus; 244 uint8_t id; 245 qemu_irq irq; 246 247 uint32_t regs[ASPEED_I2C_NEW_NUM_REG]; 248 }; 249 250 struct AspeedI2CState { 251 SysBusDevice parent_obj; 252 253 MemoryRegion iomem; 254 qemu_irq irq; 255 256 uint32_t intr_status; 257 uint32_t ctrl_global; 258 uint32_t new_clk_divider; 259 MemoryRegion pool_iomem; 260 uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; 261 262 AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; 263 MemoryRegion *dram_mr; 264 AddressSpace dram_as; 265 }; 266 267 #define TYPE_ASPEED_I2C_BUS_SLAVE "aspeed.i2c.slave" 268 OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBusSlave, ASPEED_I2C_BUS_SLAVE) 269 struct AspeedI2CBusSlave { 270 I2CSlave i2c; 271 }; 272 273 struct AspeedI2CClass { 274 SysBusDeviceClass parent_class; 275 276 uint8_t num_busses; 277 uint8_t reg_size; 278 uint8_t gap; 279 qemu_irq (*bus_get_irq)(AspeedI2CBus *); 280 281 uint64_t pool_size; 282 hwaddr pool_base; 283 uint8_t *(*bus_pool_base)(AspeedI2CBus *); 284 bool check_sram; 285 bool has_dma; 286 287 }; 288 289 static inline bool aspeed_i2c_is_new_mode(AspeedI2CState *s) 290 { 291 return FIELD_EX32(s->ctrl_global, I2C_CTRL_GLOBAL, REG_MODE); 292 } 293 294 static inline bool aspeed_i2c_bus_pkt_mode_en(AspeedI2CBus *bus) 295 { 296 if (aspeed_i2c_is_new_mode(bus->controller)) { 297 return ARRAY_FIELD_EX32(bus->regs, I2CM_CMD, PKT_OP_EN); 298 } 299 return false; 300 } 301 302 static inline uint32_t aspeed_i2c_bus_ctrl_offset(AspeedI2CBus *bus) 303 { 304 if (aspeed_i2c_is_new_mode(bus->controller)) { 305 return R_I2CC_FUN_CTRL; 306 } 307 return R_I2CD_FUN_CTRL; 308 } 309 310 static inline uint32_t aspeed_i2c_bus_cmd_offset(AspeedI2CBus *bus) 311 { 312 if (aspeed_i2c_is_new_mode(bus->controller)) { 313 return R_I2CM_CMD; 314 } 315 return R_I2CD_CMD; 316 } 317 318 static inline uint32_t aspeed_i2c_bus_dev_addr_offset(AspeedI2CBus *bus) 319 { 320 if (aspeed_i2c_is_new_mode(bus->controller)) { 321 return R_I2CS_DEV_ADDR; 322 } 323 return R_I2CD_DEV_ADDR; 324 } 325 326 static inline uint32_t aspeed_i2c_bus_intr_ctrl_offset(AspeedI2CBus *bus) 327 { 328 if (aspeed_i2c_is_new_mode(bus->controller)) { 329 return R_I2CM_INTR_CTRL; 330 } 331 return R_I2CD_INTR_CTRL; 332 } 333 334 static inline uint32_t aspeed_i2c_bus_intr_sts_offset(AspeedI2CBus *bus) 335 { 336 if (aspeed_i2c_is_new_mode(bus->controller)) { 337 return R_I2CM_INTR_STS; 338 } 339 return R_I2CD_INTR_STS; 340 } 341 342 static inline uint32_t aspeed_i2c_bus_pool_ctrl_offset(AspeedI2CBus *bus) 343 { 344 if (aspeed_i2c_is_new_mode(bus->controller)) { 345 return R_I2CC_POOL_CTRL; 346 } 347 return R_I2CD_POOL_CTRL; 348 } 349 350 static inline uint32_t aspeed_i2c_bus_byte_buf_offset(AspeedI2CBus *bus) 351 { 352 if (aspeed_i2c_is_new_mode(bus->controller)) { 353 return R_I2CC_MS_TXRX_BYTE_BUF; 354 } 355 return R_I2CD_BYTE_BUF; 356 } 357 358 static inline uint32_t aspeed_i2c_bus_dma_len_offset(AspeedI2CBus *bus) 359 { 360 if (aspeed_i2c_is_new_mode(bus->controller)) { 361 return R_I2CC_DMA_LEN; 362 } 363 return R_I2CD_DMA_LEN; 364 } 365 366 static inline uint32_t aspeed_i2c_bus_dma_addr_offset(AspeedI2CBus *bus) 367 { 368 if (aspeed_i2c_is_new_mode(bus->controller)) { 369 return R_I2CC_DMA_ADDR; 370 } 371 return R_I2CD_DMA_ADDR; 372 } 373 374 static inline bool aspeed_i2c_bus_is_master(AspeedI2CBus *bus) 375 { 376 return SHARED_ARRAY_FIELD_EX32(bus->regs, aspeed_i2c_bus_ctrl_offset(bus), 377 MASTER_EN); 378 } 379 380 static inline bool aspeed_i2c_bus_is_enabled(AspeedI2CBus *bus) 381 { 382 uint32_t ctrl_reg = aspeed_i2c_bus_ctrl_offset(bus); 383 return SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, MASTER_EN) || 384 SHARED_ARRAY_FIELD_EX32(bus->regs, ctrl_reg, SLAVE_EN); 385 } 386 387 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr); 388 389 #endif /* ASPEED_I2C_H */ 390