1 /* 2 * ASPEED AST2400 I2C Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #ifndef ASPEED_I2C_H 22 #define ASPEED_I2C_H 23 24 #include "hw/i2c/i2c.h" 25 #include "hw/sysbus.h" 26 #include "qom/object.h" 27 28 #define TYPE_ASPEED_I2C "aspeed.i2c" 29 #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" 30 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" 31 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" 32 typedef struct AspeedI2CClass AspeedI2CClass; 33 typedef struct AspeedI2CState AspeedI2CState; 34 DECLARE_OBJ_CHECKERS(AspeedI2CState, AspeedI2CClass, 35 ASPEED_I2C, TYPE_ASPEED_I2C) 36 37 #define ASPEED_I2C_NR_BUSSES 16 38 #define ASPEED_I2C_MAX_POOL_SIZE 0x800 39 40 struct AspeedI2CState; 41 42 typedef struct AspeedI2CBus { 43 struct AspeedI2CState *controller; 44 45 MemoryRegion mr; 46 47 I2CBus *bus; 48 uint8_t id; 49 qemu_irq irq; 50 51 uint32_t ctrl; 52 uint32_t timing[2]; 53 uint32_t intr_ctrl; 54 uint32_t intr_status; 55 uint32_t cmd; 56 uint32_t buf; 57 uint32_t pool_ctrl; 58 uint32_t dma_addr; 59 uint32_t dma_len; 60 } AspeedI2CBus; 61 62 struct AspeedI2CState { 63 SysBusDevice parent_obj; 64 65 MemoryRegion iomem; 66 qemu_irq irq; 67 68 uint32_t intr_status; 69 uint32_t ctrl_global; 70 MemoryRegion pool_iomem; 71 uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; 72 73 AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; 74 MemoryRegion *dram_mr; 75 AddressSpace dram_as; 76 }; 77 78 79 struct AspeedI2CClass { 80 SysBusDeviceClass parent_class; 81 82 uint8_t num_busses; 83 uint8_t reg_size; 84 uint8_t gap; 85 qemu_irq (*bus_get_irq)(AspeedI2CBus *); 86 87 uint64_t pool_size; 88 hwaddr pool_base; 89 uint8_t *(*bus_pool_base)(AspeedI2CBus *); 90 bool check_sram; 91 bool has_dma; 92 93 }; 94 95 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr); 96 97 #endif /* ASPEED_I2C_H */ 98