1 /* 2 * ASPEED AST2400 I2C Controller 3 * 4 * Copyright (C) 2016 IBM Corp. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, write to the Free Software Foundation, Inc., 18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. 19 */ 20 21 #ifndef ASPEED_I2C_H 22 #define ASPEED_I2C_H 23 24 #include "hw/i2c/i2c.h" 25 #include "hw/sysbus.h" 26 #include "qom/object.h" 27 28 #define TYPE_ASPEED_I2C "aspeed.i2c" 29 #define TYPE_ASPEED_2400_I2C TYPE_ASPEED_I2C "-ast2400" 30 #define TYPE_ASPEED_2500_I2C TYPE_ASPEED_I2C "-ast2500" 31 #define TYPE_ASPEED_2600_I2C TYPE_ASPEED_I2C "-ast2600" 32 OBJECT_DECLARE_TYPE(AspeedI2CState, AspeedI2CClass, ASPEED_I2C) 33 34 #define ASPEED_I2C_NR_BUSSES 16 35 #define ASPEED_I2C_MAX_POOL_SIZE 0x800 36 #define ASPEED_I2C_OLD_NUM_REG 11 37 38 struct AspeedI2CState; 39 40 #define TYPE_ASPEED_I2C_BUS "aspeed.i2c.bus" 41 OBJECT_DECLARE_SIMPLE_TYPE(AspeedI2CBus, ASPEED_I2C_BUS) 42 struct AspeedI2CBus { 43 SysBusDevice parent_obj; 44 45 struct AspeedI2CState *controller; 46 47 MemoryRegion mr; 48 49 I2CBus *bus; 50 uint8_t id; 51 qemu_irq irq; 52 53 uint32_t regs[ASPEED_I2C_OLD_NUM_REG]; 54 }; 55 56 struct AspeedI2CState { 57 SysBusDevice parent_obj; 58 59 MemoryRegion iomem; 60 qemu_irq irq; 61 62 uint32_t intr_status; 63 uint32_t ctrl_global; 64 MemoryRegion pool_iomem; 65 uint8_t pool[ASPEED_I2C_MAX_POOL_SIZE]; 66 67 AspeedI2CBus busses[ASPEED_I2C_NR_BUSSES]; 68 MemoryRegion *dram_mr; 69 AddressSpace dram_as; 70 }; 71 72 73 struct AspeedI2CClass { 74 SysBusDeviceClass parent_class; 75 76 uint8_t num_busses; 77 uint8_t reg_size; 78 uint8_t gap; 79 qemu_irq (*bus_get_irq)(AspeedI2CBus *); 80 81 uint64_t pool_size; 82 hwaddr pool_base; 83 uint8_t *(*bus_pool_base)(AspeedI2CBus *); 84 bool check_sram; 85 bool has_dma; 86 87 }; 88 89 I2CBus *aspeed_i2c_get_bus(AspeedI2CState *s, int busnr); 90 91 #endif /* ASPEED_I2C_H */ 92