xref: /openbmc/qemu/include/hw/i2c/allwinner-i2c.h (revision bad5cfcd)
1 /*
2  *  Allwinner I2C Bus Serial Interface registers definition
3  *
4  *  Copyright (C) 2022 Strahinja Jankovic. <strahinja.p.jankovic@gmail.com>
5  *
6  *  This file is derived from IMX I2C controller,
7  *  by Jean-Christophe DUBOIS .
8  *
9  *  This program is free software; you can redistribute it and/or modify it
10  *  under the terms of the GNU General Public License as published by the
11  *  Free Software Foundation; either version 2 of the License, or
12  *  (at your option) any later version.
13  *
14  *  This program is distributed in the hope that it will be useful, but WITHOUT
15  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16  *  FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
17  *  for more details.
18  *
19  *  You should have received a copy of the GNU General Public License along
20  *  with this program; if not, see <http://www.gnu.org/licenses/>.
21  *
22  */
23 
24 #ifndef ALLWINNER_I2C_H
25 #define ALLWINNER_I2C_H
26 
27 #include "hw/sysbus.h"
28 #include "qom/object.h"
29 
30 #define TYPE_AW_I2C "allwinner.i2c"
31 
32 /** Allwinner I2C sun6i family and newer (A31, H2+, H3, etc) */
33 #define TYPE_AW_I2C_SUN6I    TYPE_AW_I2C "-sun6i"
34 
35 OBJECT_DECLARE_SIMPLE_TYPE(AWI2CState, AW_I2C)
36 
37 #define AW_I2C_MEM_SIZE         0x24
38 
39 struct AWI2CState {
40     /*< private >*/
41     SysBusDevice parent_obj;
42 
43     /*< public >*/
44     MemoryRegion iomem;
45     I2CBus *bus;
46     qemu_irq irq;
47 
48     uint8_t addr;
49     uint8_t xaddr;
50     uint8_t data;
51     uint8_t cntr;
52     uint8_t stat;
53     uint8_t ccr;
54     uint8_t srst;
55     uint8_t efr;
56     uint8_t lcr;
57 
58     bool irq_clear_inverted;
59 };
60 
61 #endif /* ALLWINNER_I2C_H */
62