1 /* 2 * nRF51 System-on-Chip general purpose input/output register definition 3 * 4 * QEMU interface: 5 * + sysbus MMIO regions 0: GPIO registers 6 * + Unnamed GPIO inputs 0-31: Set tri-state input level for GPIO pin. 7 * Level -1: Externally Disconnected/Floating; Pull-up/down will be regarded 8 * Level 0: Input externally driven LOW 9 * Level 1: Input externally driven HIGH 10 * + Unnamed GPIO outputs 0-31: 11 * Level -1: Disconnected/Floating 12 * Level 0: Driven LOW 13 * Level 1: Driven HIGH 14 * 15 * Accuracy of the peripheral model: 16 * + The nRF51 GPIO output driver supports two modes, standard and high-current 17 * mode. These different drive modes are not modeled and handled the same. 18 * + Pin SENSEing is not modeled/implemented. 19 * 20 * Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de> 21 * 22 * This code is licensed under the GPL version 2 or later. See 23 * the COPYING file in the top-level directory. 24 * 25 */ 26 #ifndef NRF51_GPIO_H 27 #define NRF51_GPIO_H 28 29 #include "hw/sysbus.h" 30 #include "qom/object.h" 31 #define TYPE_NRF51_GPIO "nrf51_soc.gpio" 32 typedef struct NRF51GPIOState NRF51GPIOState; 33 DECLARE_INSTANCE_CHECKER(NRF51GPIOState, NRF51_GPIO, 34 TYPE_NRF51_GPIO) 35 36 #define NRF51_GPIO_PINS 32 37 38 #define NRF51_GPIO_SIZE 0x1000 39 40 #define NRF51_GPIO_REG_OUT 0x504 41 #define NRF51_GPIO_REG_OUTSET 0x508 42 #define NRF51_GPIO_REG_OUTCLR 0x50C 43 #define NRF51_GPIO_REG_IN 0x510 44 #define NRF51_GPIO_REG_DIR 0x514 45 #define NRF51_GPIO_REG_DIRSET 0x518 46 #define NRF51_GPIO_REG_DIRCLR 0x51C 47 #define NRF51_GPIO_REG_CNF_START 0x700 48 #define NRF51_GPIO_REG_CNF_END 0x77C 49 50 #define NRF51_GPIO_PULLDOWN 1 51 #define NRF51_GPIO_PULLUP 3 52 53 struct NRF51GPIOState { 54 SysBusDevice parent_obj; 55 56 MemoryRegion mmio; 57 qemu_irq irq; 58 59 uint32_t out; 60 uint32_t in; 61 uint32_t in_mask; 62 uint32_t dir; 63 uint32_t cnf[NRF51_GPIO_PINS]; 64 65 uint32_t old_out; 66 uint32_t old_out_connected; 67 68 qemu_irq output[NRF51_GPIO_PINS]; 69 }; 70 71 72 #endif 73