1 /* 2 * i.MX processors GPIO registers definition. 3 * 4 * Copyright (C) 2015 Jean-Christophe Dubois <jcd@tribudubois.net> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 or 9 * (at your option) version 3 of the License. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License along 17 * with this program; if not, see <http://www.gnu.org/licenses/>. 18 */ 19 20 #ifndef __IMX_GPIO_H_ 21 #define __IMX_GPIO_H_ 22 23 #include <hw/sysbus.h> 24 25 #define TYPE_IMX_GPIO "imx.gpio" 26 #define IMX_GPIO(obj) OBJECT_CHECK(IMXGPIOState, (obj), TYPE_IMX_GPIO) 27 28 #define IMX_GPIO_MEM_SIZE 0x20 29 30 /* i.MX GPIO memory map */ 31 #define DR_ADDR 0x00 /* DATA REGISTER */ 32 #define GDIR_ADDR 0x04 /* DIRECTION REGISTER */ 33 #define PSR_ADDR 0x08 /* PAD STATUS REGISTER */ 34 #define ICR1_ADDR 0x0c /* INTERRUPT CONFIGURATION REGISTER 1 */ 35 #define ICR2_ADDR 0x10 /* INTERRUPT CONFIGURATION REGISTER 2 */ 36 #define IMR_ADDR 0x14 /* INTERRUPT MASK REGISTER */ 37 #define ISR_ADDR 0x18 /* INTERRUPT STATUS REGISTER */ 38 #define EDGE_SEL_ADDR 0x1c /* EDGE SEL REGISTER */ 39 40 #define IMX_GPIO_PIN_COUNT 32 41 42 typedef struct IMXGPIOState { 43 /*< private >*/ 44 SysBusDevice parent_obj; 45 46 /*< public >*/ 47 MemoryRegion iomem; 48 49 uint32_t dr; 50 uint32_t gdir; 51 uint32_t psr; 52 uint64_t icr; 53 uint32_t imr; 54 uint32_t isr; 55 bool has_edge_sel; 56 uint32_t edge_sel; 57 bool has_upper_pin_irq; 58 59 qemu_irq irq[2]; 60 qemu_irq output[IMX_GPIO_PIN_COUNT]; 61 } IMXGPIOState; 62 63 #endif /* __IMX_GPIO_H_ */ 64