1 /* 2 * ASPEED GPIO Controller 3 * 4 * Copyright (C) 2017-2018 IBM Corp. 5 * 6 * This code is licensed under the GPL version 2 or later. See 7 * the COPYING file in the top-level directory. 8 */ 9 10 #ifndef ASPEED_GPIO_H 11 #define ASPEED_GPIO_H 12 13 #include "hw/sysbus.h" 14 #include "qom/object.h" 15 16 #define TYPE_ASPEED_GPIO "aspeed.gpio" 17 OBJECT_DECLARE_TYPE(AspeedGPIOState, AspeedGPIOClass, ASPEED_GPIO) 18 19 #define ASPEED_GPIO_MAX_NR_SETS 8 20 #define ASPEED_REGS_PER_BANK 14 21 #define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS) 22 #define ASPEED_GPIO_NR_PINS 228 23 #define ASPEED_GROUPS_PER_SET 4 24 #define ASPEED_GPIO_NR_DEBOUNCE_REGS 3 25 #define ASPEED_CHARS_PER_GROUP_LABEL 4 26 27 typedef struct GPIOSets GPIOSets; 28 29 typedef struct GPIOSetProperties { 30 uint32_t input; 31 uint32_t output; 32 char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL]; 33 } GPIOSetProperties; 34 35 enum GPIORegType { 36 gpio_not_a_reg, 37 gpio_reg_data_value, 38 gpio_reg_direction, 39 gpio_reg_int_enable, 40 gpio_reg_int_sens_0, 41 gpio_reg_int_sens_1, 42 gpio_reg_int_sens_2, 43 gpio_reg_int_status, 44 gpio_reg_reset_tolerant, 45 gpio_reg_debounce_1, 46 gpio_reg_debounce_2, 47 gpio_reg_cmd_source_0, 48 gpio_reg_cmd_source_1, 49 gpio_reg_data_read, 50 gpio_reg_input_mask, 51 }; 52 53 typedef struct AspeedGPIOReg { 54 uint16_t set_idx; 55 enum GPIORegType type; 56 } AspeedGPIOReg; 57 58 struct AspeedGPIOClass { 59 SysBusDevice parent_obj; 60 const GPIOSetProperties *props; 61 uint32_t nr_gpio_pins; 62 uint32_t nr_gpio_sets; 63 uint32_t gap; 64 const AspeedGPIOReg *reg_table; 65 }; 66 67 struct AspeedGPIOState { 68 /* <private> */ 69 SysBusDevice parent; 70 71 /*< public >*/ 72 MemoryRegion iomem; 73 int pending; 74 qemu_irq irq; 75 qemu_irq gpios[ASPEED_GPIO_NR_PINS]; 76 77 /* Parallel GPIO Registers */ 78 uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS]; 79 struct GPIOSets { 80 uint32_t data_value; /* Reflects pin values */ 81 uint32_t data_read; /* Contains last value written to data value */ 82 uint32_t direction; 83 uint32_t int_enable; 84 uint32_t int_sens_0; 85 uint32_t int_sens_1; 86 uint32_t int_sens_2; 87 uint32_t int_status; 88 uint32_t reset_tol; 89 uint32_t cmd_source_0; 90 uint32_t cmd_source_1; 91 uint32_t debounce_1; 92 uint32_t debounce_2; 93 uint32_t input_mask; 94 } sets[ASPEED_GPIO_MAX_NR_SETS]; 95 }; 96 97 #endif /* _ASPEED_GPIO_H_ */ 98