1 /* 2 * QEMU CXL PCI interfaces 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_PCI_H 11 #define CXL_PCI_H 12 13 #include "qemu/compiler.h" 14 15 #define CXL_VENDOR_ID 0x1e98 16 17 #define PCIE_DVSEC_HEADER1_OFFSET 0x4 /* Offset from start of extend cap */ 18 #define PCIE_DVSEC_ID_OFFSET 0x8 19 20 #define PCIE_CXL_DEVICE_DVSEC_LENGTH 0x38 21 #define PCIE_CXL1_DEVICE_DVSEC_REVID 0 22 #define PCIE_CXL2_DEVICE_DVSEC_REVID 1 23 24 #define EXTENSIONS_PORT_DVSEC_LENGTH 0x28 25 #define EXTENSIONS_PORT_DVSEC_REVID 0 26 27 #define GPF_PORT_DVSEC_LENGTH 0x10 28 #define GPF_PORT_DVSEC_REVID 0 29 30 #define GPF_DEVICE_DVSEC_LENGTH 0x10 31 #define GPF_DEVICE_DVSEC_REVID 0 32 33 #define PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0 0x14 34 #define PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0 1 35 36 #define REG_LOC_DVSEC_LENGTH 0x24 37 #define REG_LOC_DVSEC_REVID 0 38 39 enum { 40 PCIE_CXL_DEVICE_DVSEC = 0, 41 NON_CXL_FUNCTION_MAP_DVSEC = 2, 42 EXTENSIONS_PORT_DVSEC = 3, 43 GPF_PORT_DVSEC = 4, 44 GPF_DEVICE_DVSEC = 5, 45 PCIE_FLEXBUS_PORT_DVSEC = 7, 46 REG_LOC_DVSEC = 8, 47 MLD_DVSEC = 9, 48 CXL20_MAX_DVSEC 49 }; 50 51 typedef struct DVSECHeader { 52 uint32_t cap_hdr; 53 uint32_t dv_hdr1; 54 uint16_t dv_hdr2; 55 } QEMU_PACKED DVSECHeader; 56 QEMU_BUILD_BUG_ON(sizeof(DVSECHeader) != 10); 57 58 /* 59 * CXL 2.0 devices must implement certain DVSEC IDs, and can [optionally] 60 * implement others. 61 * 62 * CXL 2.0 Device: 0, [2], 5, 8 63 * CXL 2.0 RP: 3, 4, 7, 8 64 * CXL 2.0 Upstream Port: [2], 7, 8 65 * CXL 2.0 Downstream Port: 3, 4, 7, 8 66 */ 67 68 /* CXL 2.0 - 8.1.3 (ID 0001) */ 69 typedef struct CXLDVSECDevice { 70 DVSECHeader hdr; 71 uint16_t cap; 72 uint16_t ctrl; 73 uint16_t status; 74 uint16_t ctrl2; 75 uint16_t status2; 76 uint16_t lock; 77 uint16_t cap2; 78 uint32_t range1_size_hi; 79 uint32_t range1_size_lo; 80 uint32_t range1_base_hi; 81 uint32_t range1_base_lo; 82 uint32_t range2_size_hi; 83 uint32_t range2_size_lo; 84 uint32_t range2_base_hi; 85 uint32_t range2_base_lo; 86 } CXLDVSECDevice; 87 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) != 0x38); 88 89 /* CXL 2.0 - 8.1.5 (ID 0003) */ 90 typedef struct CXLDVSECPortExtensions { 91 DVSECHeader hdr; 92 uint16_t status; 93 uint16_t control; 94 uint8_t alt_bus_base; 95 uint8_t alt_bus_limit; 96 uint16_t alt_memory_base; 97 uint16_t alt_memory_limit; 98 uint16_t alt_prefetch_base; 99 uint16_t alt_prefetch_limit; 100 uint32_t alt_prefetch_base_high; 101 uint32_t alt_prefetch_limit_high; 102 uint32_t rcrb_base; 103 uint32_t rcrb_base_high; 104 } CXLDVSECPortExtensions; 105 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExtensions) != 0x28); 106 107 #define PORT_CONTROL_OFFSET 0xc 108 #define PORT_CONTROL_UNMASK_SBR 1 109 #define PORT_CONTROL_ALT_MEMID_EN 4 110 111 /* CXL 2.0 - 8.1.6 GPF DVSEC (ID 0004) */ 112 typedef struct CXLDVSECPortGPF { 113 DVSECHeader hdr; 114 uint16_t rsvd; 115 uint16_t phase1_ctrl; 116 uint16_t phase2_ctrl; 117 } CXLDVSECPortGPF; 118 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortGPF) != 0x10); 119 120 /* CXL 2.0 - 8.1.7 GPF DVSEC for CXL Device */ 121 typedef struct CXLDVSECDeviceGPF { 122 DVSECHeader hdr; 123 uint16_t phase2_duration; 124 uint32_t phase2_power; 125 } CXLDVSECDeviceGPF; 126 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDeviceGPF) != 0x10); 127 128 /* CXL 2.0 - 8.1.8/8.2.1.3 Flex Bus DVSEC (ID 0007) */ 129 typedef struct CXLDVSECPortFlexBus { 130 DVSECHeader hdr; 131 uint16_t cap; 132 uint16_t ctrl; 133 uint16_t status; 134 uint32_t rcvd_mod_ts_data_phase1; 135 } CXLDVSECPortFlexBus; 136 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortFlexBus) != 0x14); 137 138 /* CXL 2.0 - 8.1.9 Register Locator DVSEC (ID 0008) */ 139 typedef struct CXLDVSECRegisterLocator { 140 DVSECHeader hdr; 141 uint16_t rsvd; 142 uint32_t reg0_base_lo; 143 uint32_t reg0_base_hi; 144 uint32_t reg1_base_lo; 145 uint32_t reg1_base_hi; 146 uint32_t reg2_base_lo; 147 uint32_t reg2_base_hi; 148 } CXLDVSECRegisterLocator; 149 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECRegisterLocator) != 0x24); 150 151 /* BAR Equivalence Indicator */ 152 #define BEI_BAR_10H 0 153 #define BEI_BAR_14H 1 154 #define BEI_BAR_18H 2 155 #define BEI_BAR_1cH 3 156 #define BEI_BAR_20H 4 157 #define BEI_BAR_24H 5 158 159 /* Register Block Identifier */ 160 #define RBI_EMPTY 0 161 #define RBI_COMPONENT_REG (1 << 8) 162 #define RBI_BAR_VIRT_ACL (2 << 8) 163 #define RBI_CXL_DEVICE_REG (3 << 8) 164 165 #endif 166