1 /* 2 * QEMU CXL PCI interfaces 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_PCI_H 11 #define CXL_PCI_H 12 13 14 #define CXL_VENDOR_ID 0x1e98 15 16 #define PCIE_DVSEC_HEADER1_OFFSET 0x4 /* Offset from start of extend cap */ 17 #define PCIE_DVSEC_ID_OFFSET 0x8 18 19 #define PCIE_CXL_DEVICE_DVSEC_LENGTH 0x38 20 #define PCIE_CXL1_DEVICE_DVSEC_REVID 0 21 #define PCIE_CXL2_DEVICE_DVSEC_REVID 1 22 23 #define EXTENSIONS_PORT_DVSEC_LENGTH 0x28 24 #define EXTENSIONS_PORT_DVSEC_REVID 0 25 26 #define GPF_PORT_DVSEC_LENGTH 0x10 27 #define GPF_PORT_DVSEC_REVID 0 28 29 #define GPF_DEVICE_DVSEC_LENGTH 0x10 30 #define GPF_DEVICE_DVSEC_REVID 0 31 32 #define PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0 0x14 33 #define PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0 1 34 35 #define REG_LOC_DVSEC_LENGTH 0x24 36 #define REG_LOC_DVSEC_REVID 0 37 38 enum { 39 PCIE_CXL_DEVICE_DVSEC = 0, 40 NON_CXL_FUNCTION_MAP_DVSEC = 2, 41 EXTENSIONS_PORT_DVSEC = 3, 42 GPF_PORT_DVSEC = 4, 43 GPF_DEVICE_DVSEC = 5, 44 PCIE_FLEXBUS_PORT_DVSEC = 7, 45 REG_LOC_DVSEC = 8, 46 MLD_DVSEC = 9, 47 CXL20_MAX_DVSEC 48 }; 49 50 typedef struct DVSECHeader { 51 uint32_t cap_hdr; 52 uint32_t dv_hdr1; 53 uint16_t dv_hdr2; 54 } QEMU_PACKED DVSECHeader; 55 QEMU_BUILD_BUG_ON(sizeof(DVSECHeader) != 10); 56 57 /* 58 * CXL 2.0 devices must implement certain DVSEC IDs, and can [optionally] 59 * implement others. 60 * 61 * CXL 2.0 Device: 0, [2], 5, 8 62 * CXL 2.0 RP: 3, 4, 7, 8 63 * CXL 2.0 Upstream Port: [2], 7, 8 64 * CXL 2.0 Downstream Port: 3, 4, 7, 8 65 */ 66 67 /* CXL 2.0 - 8.1.3 (ID 0001) */ 68 typedef struct CXLDVSECDevice { 69 DVSECHeader hdr; 70 uint16_t cap; 71 uint16_t ctrl; 72 uint16_t status; 73 uint16_t ctrl2; 74 uint16_t status2; 75 uint16_t lock; 76 uint16_t cap2; 77 uint32_t range1_size_hi; 78 uint32_t range1_size_lo; 79 uint32_t range1_base_hi; 80 uint32_t range1_base_lo; 81 uint32_t range2_size_hi; 82 uint32_t range2_size_lo; 83 uint32_t range2_base_hi; 84 uint32_t range2_base_lo; 85 } CXLDVSECDevice; 86 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) != 0x38); 87 88 /* CXL 2.0 - 8.1.5 (ID 0003) */ 89 typedef struct CXLDVSECPortExtensions { 90 DVSECHeader hdr; 91 uint16_t status; 92 uint16_t control; 93 uint8_t alt_bus_base; 94 uint8_t alt_bus_limit; 95 uint16_t alt_memory_base; 96 uint16_t alt_memory_limit; 97 uint16_t alt_prefetch_base; 98 uint16_t alt_prefetch_limit; 99 uint32_t alt_prefetch_base_high; 100 uint32_t alt_prefetch_limit_high; 101 uint32_t rcrb_base; 102 uint32_t rcrb_base_high; 103 } CXLDVSECPortExtensions; 104 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExtensions) != 0x28); 105 106 #define PORT_CONTROL_OFFSET 0xc 107 #define PORT_CONTROL_UNMASK_SBR 1 108 #define PORT_CONTROL_ALT_MEMID_EN 4 109 110 /* CXL 2.0 - 8.1.6 GPF DVSEC (ID 0004) */ 111 typedef struct CXLDVSECPortGPF { 112 DVSECHeader hdr; 113 uint16_t rsvd; 114 uint16_t phase1_ctrl; 115 uint16_t phase2_ctrl; 116 } CXLDVSECPortGPF; 117 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortGPF) != 0x10); 118 119 /* CXL 2.0 - 8.1.7 GPF DVSEC for CXL Device */ 120 typedef struct CXLDVSECDeviceGPF { 121 DVSECHeader hdr; 122 uint16_t phase2_duration; 123 uint32_t phase2_power; 124 } CXLDVSECDeviceGPF; 125 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDeviceGPF) != 0x10); 126 127 /* CXL 2.0 - 8.1.8/8.2.1.3 Flex Bus DVSEC (ID 0007) */ 128 typedef struct CXLDVSECPortFlexBus { 129 DVSECHeader hdr; 130 uint16_t cap; 131 uint16_t ctrl; 132 uint16_t status; 133 uint32_t rcvd_mod_ts_data_phase1; 134 } CXLDVSECPortFlexBus; 135 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortFlexBus) != 0x14); 136 137 /* CXL 2.0 - 8.1.9 Register Locator DVSEC (ID 0008) */ 138 typedef struct CXLDVSECRegisterLocator { 139 DVSECHeader hdr; 140 uint16_t rsvd; 141 uint32_t reg0_base_lo; 142 uint32_t reg0_base_hi; 143 uint32_t reg1_base_lo; 144 uint32_t reg1_base_hi; 145 uint32_t reg2_base_lo; 146 uint32_t reg2_base_hi; 147 } CXLDVSECRegisterLocator; 148 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECRegisterLocator) != 0x24); 149 150 /* BAR Equivalence Indicator */ 151 #define BEI_BAR_10H 0 152 #define BEI_BAR_14H 1 153 #define BEI_BAR_18H 2 154 #define BEI_BAR_1cH 3 155 #define BEI_BAR_20H 4 156 #define BEI_BAR_24H 5 157 158 /* Register Block Identifier */ 159 #define RBI_EMPTY 0 160 #define RBI_COMPONENT_REG (1 << 8) 161 #define RBI_BAR_VIRT_ACL (2 << 8) 162 #define RBI_CXL_DEVICE_REG (3 << 8) 163 164 #endif 165