1 /* 2 * QEMU CXL PCI interfaces 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_PCI_H 11 #define CXL_PCI_H 12 13 #include "qemu/compiler.h" 14 #include "hw/pci/pci.h" 15 #include "hw/pci/pcie.h" 16 17 #define CXL_VENDOR_ID 0x1e98 18 19 #define PCIE_DVSEC_HEADER1_OFFSET 0x4 /* Offset from start of extend cap */ 20 #define PCIE_DVSEC_ID_OFFSET 0x8 21 22 #define PCIE_CXL_DEVICE_DVSEC_LENGTH 0x38 23 #define PCIE_CXL1_DEVICE_DVSEC_REVID 0 24 #define PCIE_CXL2_DEVICE_DVSEC_REVID 1 25 26 #define EXTENSIONS_PORT_DVSEC_LENGTH 0x28 27 #define EXTENSIONS_PORT_DVSEC_REVID 0 28 29 #define GPF_PORT_DVSEC_LENGTH 0x10 30 #define GPF_PORT_DVSEC_REVID 0 31 32 #define GPF_DEVICE_DVSEC_LENGTH 0x10 33 #define GPF_DEVICE_DVSEC_REVID 0 34 35 #define PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0 0x14 36 #define PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0 1 37 38 #define REG_LOC_DVSEC_LENGTH 0x24 39 #define REG_LOC_DVSEC_REVID 0 40 41 enum { 42 PCIE_CXL_DEVICE_DVSEC = 0, 43 NON_CXL_FUNCTION_MAP_DVSEC = 2, 44 EXTENSIONS_PORT_DVSEC = 3, 45 GPF_PORT_DVSEC = 4, 46 GPF_DEVICE_DVSEC = 5, 47 PCIE_FLEXBUS_PORT_DVSEC = 7, 48 REG_LOC_DVSEC = 8, 49 MLD_DVSEC = 9, 50 CXL20_MAX_DVSEC 51 }; 52 53 typedef struct DVSECHeader { 54 uint32_t cap_hdr; 55 uint32_t dv_hdr1; 56 uint16_t dv_hdr2; 57 } QEMU_PACKED DVSECHeader; 58 QEMU_BUILD_BUG_ON(sizeof(DVSECHeader) != 10); 59 60 /* 61 * CXL 2.0 devices must implement certain DVSEC IDs, and can [optionally] 62 * implement others. 63 * 64 * CXL 2.0 Device: 0, [2], 5, 8 65 * CXL 2.0 RP: 3, 4, 7, 8 66 * CXL 2.0 Upstream Port: [2], 7, 8 67 * CXL 2.0 Downstream Port: 3, 4, 7, 8 68 */ 69 70 /* CXL 2.0 - 8.1.3 (ID 0001) */ 71 typedef struct CXLDVSECDevice { 72 DVSECHeader hdr; 73 uint16_t cap; 74 uint16_t ctrl; 75 uint16_t status; 76 uint16_t ctrl2; 77 uint16_t status2; 78 uint16_t lock; 79 uint16_t cap2; 80 uint32_t range1_size_hi; 81 uint32_t range1_size_lo; 82 uint32_t range1_base_hi; 83 uint32_t range1_base_lo; 84 uint32_t range2_size_hi; 85 uint32_t range2_size_lo; 86 uint32_t range2_base_hi; 87 uint32_t range2_base_lo; 88 } CXLDVSECDevice; 89 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) != 0x38); 90 91 /* CXL 2.0 - 8.1.5 (ID 0003) */ 92 typedef struct CXLDVSECPortExtensions { 93 DVSECHeader hdr; 94 uint16_t status; 95 uint16_t control; 96 uint8_t alt_bus_base; 97 uint8_t alt_bus_limit; 98 uint16_t alt_memory_base; 99 uint16_t alt_memory_limit; 100 uint16_t alt_prefetch_base; 101 uint16_t alt_prefetch_limit; 102 uint32_t alt_prefetch_base_high; 103 uint32_t alt_prefetch_limit_high; 104 uint32_t rcrb_base; 105 uint32_t rcrb_base_high; 106 } CXLDVSECPortExtensions; 107 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExtensions) != 0x28); 108 109 #define PORT_CONTROL_OFFSET 0xc 110 #define PORT_CONTROL_UNMASK_SBR 1 111 #define PORT_CONTROL_ALT_MEMID_EN 4 112 113 /* CXL 2.0 - 8.1.6 GPF DVSEC (ID 0004) */ 114 typedef struct CXLDVSECPortGPF { 115 DVSECHeader hdr; 116 uint16_t rsvd; 117 uint16_t phase1_ctrl; 118 uint16_t phase2_ctrl; 119 } CXLDVSECPortGPF; 120 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortGPF) != 0x10); 121 122 /* CXL 2.0 - 8.1.7 GPF DVSEC for CXL Device */ 123 typedef struct CXLDVSECDeviceGPF { 124 DVSECHeader hdr; 125 uint16_t phase2_duration; 126 uint32_t phase2_power; 127 } CXLDVSECDeviceGPF; 128 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDeviceGPF) != 0x10); 129 130 /* CXL 2.0 - 8.1.8/8.2.1.3 Flex Bus DVSEC (ID 0007) */ 131 typedef struct CXLDVSECPortFlexBus { 132 DVSECHeader hdr; 133 uint16_t cap; 134 uint16_t ctrl; 135 uint16_t status; 136 uint32_t rcvd_mod_ts_data_phase1; 137 } CXLDVSECPortFlexBus; 138 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortFlexBus) != 0x14); 139 140 /* CXL 2.0 - 8.1.9 Register Locator DVSEC (ID 0008) */ 141 typedef struct CXLDVSECRegisterLocator { 142 DVSECHeader hdr; 143 uint16_t rsvd; 144 uint32_t reg0_base_lo; 145 uint32_t reg0_base_hi; 146 uint32_t reg1_base_lo; 147 uint32_t reg1_base_hi; 148 uint32_t reg2_base_lo; 149 uint32_t reg2_base_hi; 150 } CXLDVSECRegisterLocator; 151 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECRegisterLocator) != 0x24); 152 153 /* BAR Equivalence Indicator */ 154 #define BEI_BAR_10H 0 155 #define BEI_BAR_14H 1 156 #define BEI_BAR_18H 2 157 #define BEI_BAR_1cH 3 158 #define BEI_BAR_20H 4 159 #define BEI_BAR_24H 5 160 161 /* Register Block Identifier */ 162 #define RBI_EMPTY 0 163 #define RBI_COMPONENT_REG (1 << 8) 164 #define RBI_BAR_VIRT_ACL (2 << 8) 165 #define RBI_CXL_DEVICE_REG (3 << 8) 166 167 #endif 168