1 /* 2 * QEMU CXL PCI interfaces 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_PCI_H 11 #define CXL_PCI_H 12 13 14 #define CXL_VENDOR_ID 0x1e98 15 16 #define PCIE_DVSEC_HEADER1_OFFSET 0x4 /* Offset from start of extend cap */ 17 #define PCIE_DVSEC_ID_OFFSET 0x8 18 19 #define PCIE_CXL_DEVICE_DVSEC_LENGTH 0x3C 20 #define PCIE_CXL31_DEVICE_DVSEC_REVID 3 21 22 #define EXTENSIONS_PORT_DVSEC_LENGTH 0x28 23 #define EXTENSIONS_PORT_DVSEC_REVID 0 24 25 #define GPF_PORT_DVSEC_LENGTH 0x10 26 #define GPF_PORT_DVSEC_REVID 0 27 28 #define GPF_DEVICE_DVSEC_LENGTH 0x10 29 #define GPF_DEVICE_DVSEC_REVID 0 30 31 #define PCIE_CXL3_FLEXBUS_PORT_DVSEC_LENGTH 0x20 32 #define PCIE_CXL3_FLEXBUS_PORT_DVSEC_REVID 2 33 34 #define REG_LOC_DVSEC_LENGTH 0x24 35 #define REG_LOC_DVSEC_REVID 0 36 37 enum { 38 PCIE_CXL_DEVICE_DVSEC = 0, 39 NON_CXL_FUNCTION_MAP_DVSEC = 2, 40 EXTENSIONS_PORT_DVSEC = 3, 41 GPF_PORT_DVSEC = 4, 42 GPF_DEVICE_DVSEC = 5, 43 PCIE_FLEXBUS_PORT_DVSEC = 7, 44 REG_LOC_DVSEC = 8, 45 MLD_DVSEC = 9, 46 CXL20_MAX_DVSEC 47 }; 48 49 typedef struct DVSECHeader { 50 uint32_t cap_hdr; 51 uint32_t dv_hdr1; 52 uint16_t dv_hdr2; 53 } QEMU_PACKED DVSECHeader; 54 QEMU_BUILD_BUG_ON(sizeof(DVSECHeader) != 10); 55 56 /* 57 * CXL r3.1 Table 8-2: CXL DVSEC ID Assignment 58 * Devices must implement certain DVSEC IDs, and can [optionally] 59 * implement others. 60 * (x) - IDs in Table 8-2. 61 * 62 * CXL RCD (D1): 0, [2], [5], 7, [8], A - Not emulated yet 63 * CXL RCD USP (UP1): 7, [8] - Not emulated yet 64 * CXL RCH DSP (DP1): 7, [8] 65 * CXL SLD (D2): 0, [2], 5, 7, 8, [A] 66 * CXL LD (LD): 0, [2], 5, 7, 8 67 * CXL RP (R): 3, 4, 7, 8 68 * CXL Switch USP (USP): [2], 7, 8 69 * CXL Switch DSP (DSP): 3, 4, 7, 8 70 * FM-Owned LD (FMLD): 0, [2], 7, 8, 9 71 */ 72 73 /* 74 * CXL r3.1 Section 8.1.3: PCIe DVSEC for Devices 75 * DVSEC ID: 0, Revision: 3 76 */ 77 typedef struct CXLDVSECDevice { 78 DVSECHeader hdr; 79 uint16_t cap; 80 uint16_t ctrl; 81 uint16_t status; 82 uint16_t ctrl2; 83 uint16_t status2; 84 uint16_t lock; 85 uint16_t cap2; 86 uint32_t range1_size_hi; 87 uint32_t range1_size_lo; 88 uint32_t range1_base_hi; 89 uint32_t range1_base_lo; 90 uint32_t range2_size_hi; 91 uint32_t range2_size_lo; 92 uint32_t range2_base_hi; 93 uint32_t range2_base_lo; 94 uint16_t cap3; 95 uint16_t resv; 96 } QEMU_PACKED CXLDVSECDevice; 97 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDevice) != PCIE_CXL_DEVICE_DVSEC_LENGTH); 98 99 /* 100 * CXL r3.1 Section 8.1.5: CXL Extensions DVSEC for Ports 101 * DVSEC ID: 3, Revision: 0 102 */ 103 typedef struct CXLDVSECPortExt { 104 DVSECHeader hdr; 105 uint16_t status; 106 uint16_t control; 107 uint8_t alt_bus_base; 108 uint8_t alt_bus_limit; 109 uint16_t alt_memory_base; 110 uint16_t alt_memory_limit; 111 uint16_t alt_prefetch_base; 112 uint16_t alt_prefetch_limit; 113 uint32_t alt_prefetch_base_high; 114 uint32_t alt_prefetch_limit_high; 115 uint32_t rcrb_base; 116 uint32_t rcrb_base_high; 117 } CXLDVSECPortExt; 118 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortExt) != 0x28); 119 120 #define PORT_CONTROL_OFFSET 0xc 121 #define PORT_CONTROL_UNMASK_SBR 1 122 #define PORT_CONTROL_ALT_MEMID_EN 4 123 124 /* 125 * CXL r3.1 Section 8.1.6: GPF DVSEC for CXL Port 126 * DVSEC ID: 4, Revision: 0 127 */ 128 typedef struct CXLDVSECPortGPF { 129 DVSECHeader hdr; 130 uint16_t rsvd; 131 uint16_t phase1_ctrl; 132 uint16_t phase2_ctrl; 133 } CXLDVSECPortGPF; 134 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortGPF) != 0x10); 135 136 /* 137 * CXL r3.1 Section 8.1.7: GPF DVSEC for CXL Device 138 * DVSEC ID: 5, Revision 0 139 */ 140 typedef struct CXLDVSECDeviceGPF { 141 DVSECHeader hdr; 142 uint16_t phase2_duration; 143 uint32_t phase2_power; 144 } CXLDVSECDeviceGPF; 145 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECDeviceGPF) != 0x10); 146 147 /* 148 * CXL r3.1 Section 8.1.8: PCIe DVSEC for Flex Bus Port 149 * CXL r3.1 Section 8.2.1.3: Flex Bus Port DVSEC 150 * DVSEC ID: 7, Revision 2 151 */ 152 typedef struct CXLDVSECPortFlexBus { 153 DVSECHeader hdr; 154 uint16_t cap; 155 uint16_t ctrl; 156 uint16_t status; 157 uint32_t rcvd_mod_ts_data_phase1; 158 uint32_t cap2; 159 uint32_t ctrl2; 160 uint32_t status2; 161 } CXLDVSECPortFlexBus; 162 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECPortFlexBus) != 0x20); 163 164 /* 165 * CXL r3.1 Section 8.1.9: Register Locator DVSEC 166 * DVSEC ID: 8, Revision 0 167 */ 168 typedef struct CXLDVSECRegisterLocator { 169 DVSECHeader hdr; 170 uint16_t rsvd; 171 uint32_t reg0_base_lo; 172 uint32_t reg0_base_hi; 173 uint32_t reg1_base_lo; 174 uint32_t reg1_base_hi; 175 uint32_t reg2_base_lo; 176 uint32_t reg2_base_hi; 177 } CXLDVSECRegisterLocator; 178 QEMU_BUILD_BUG_ON(sizeof(CXLDVSECRegisterLocator) != 0x24); 179 180 /* BAR Equivalence Indicator */ 181 #define BEI_BAR_10H 0 182 #define BEI_BAR_14H 1 183 #define BEI_BAR_18H 2 184 #define BEI_BAR_1cH 3 185 #define BEI_BAR_20H 4 186 #define BEI_BAR_24H 5 187 188 /* Register Block Identifier */ 189 #define RBI_EMPTY 0 190 #define RBI_COMPONENT_REG (1 << 8) 191 #define RBI_BAR_VIRT_ACL (2 << 8) 192 #define RBI_CXL_DEVICE_REG (3 << 8) 193 194 #endif 195