1 /* 2 * QEMU CXL Devices 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_DEVICE_H 11 #define CXL_DEVICE_H 12 13 #include "hw/cxl/cxl_component.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/register.h" 16 #include "hw/cxl/cxl_events.h" 17 18 /* 19 * The following is how a CXL device's Memory Device registers are laid out. 20 * The only requirement from the spec is that the capabilities array and the 21 * capability headers start at offset 0 and are contiguously packed. The headers 22 * themselves provide offsets to the register fields. For this emulation, the 23 * actual registers * will start at offset 0x80 (m == 0x80). No secondary 24 * mailbox is implemented which means that the offset of the start of the 25 * mailbox payload (n) is given by 26 * n = m + sizeof(mailbox registers) + sizeof(device registers). 27 * 28 * +---------------------------------+ 29 * | | 30 * | Memory Device Registers | 31 * | | 32 * n + PAYLOAD_SIZE_MAX ----------------------------------- 33 * ^ | | 34 * | | | 35 * | | | 36 * | | | 37 * | | | 38 * | | Mailbox Payload | 39 * | | | 40 * | | | 41 * | | | 42 * n ----------------------------------- 43 * ^ | Mailbox Registers | 44 * | | | 45 * | ----------------------------------- 46 * | | | 47 * | | Device Registers | 48 * | | | 49 * m ----------------------------------> 50 * ^ | Memory Device Capability Header| 51 * | ----------------------------------- 52 * | | Mailbox Capability Header | 53 * | ----------------------------------- 54 * | | Device Capability Header | 55 * | ----------------------------------- 56 * | | Device Cap Array Register | 57 * 0 +---------------------------------+ 58 * 59 */ 60 61 /* CXL r3.1 Figure 8-12: CXL Device Registers */ 62 #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 63 /* CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register */ 64 #define CXL_DEVICE_CAP_REG_SIZE 0x10 65 66 /* 67 * CXL r3.1 Section 8.2.8.2.1: CXL Device Capabilities + 68 * CXL r3.1 Section 8.2.8.5: Memory Device Capabilities 69 */ 70 #define CXL_DEVICE_CAPS_MAX 4 71 #define CXL_CAPS_SIZE \ 72 (CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */ 73 74 #define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */ 75 /* 76 * CXL r3.1 Section 8.2.8.3: Device Status Registers 77 * As it is the only Device Status Register in CXL r3.1 78 */ 79 #define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8 80 81 #define CXL_MAILBOX_REGISTERS_OFFSET \ 82 (CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH) 83 /* CXL r3.1 Figure 8-13: Mailbox Registers */ 84 #define CXL_MAILBOX_REGISTERS_SIZE 0x20 85 #define CXL_MAILBOX_PAYLOAD_SHIFT 11 86 #define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT) 87 #define CXL_MAILBOX_REGISTERS_LENGTH \ 88 (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) 89 90 #define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \ 91 (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH) 92 #define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8 93 94 #define CXL_MMIO_SIZE \ 95 (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH + \ 96 CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH) 97 98 /* CXL r3.1 Table 8-34: Command Return Codes */ 99 typedef enum { 100 CXL_MBOX_SUCCESS = 0x0, 101 CXL_MBOX_BG_STARTED = 0x1, 102 CXL_MBOX_INVALID_INPUT = 0x2, 103 CXL_MBOX_UNSUPPORTED = 0x3, 104 CXL_MBOX_INTERNAL_ERROR = 0x4, 105 CXL_MBOX_RETRY_REQUIRED = 0x5, 106 CXL_MBOX_BUSY = 0x6, 107 CXL_MBOX_MEDIA_DISABLED = 0x7, 108 CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8, 109 CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9, 110 CXL_MBOX_FW_AUTH_FAILED = 0xa, 111 CXL_MBOX_FW_INVALID_SLOT = 0xb, 112 CXL_MBOX_FW_ROLLEDBACK = 0xc, 113 CXL_MBOX_FW_REST_REQD = 0xd, 114 CXL_MBOX_INVALID_HANDLE = 0xe, 115 CXL_MBOX_INVALID_PA = 0xf, 116 CXL_MBOX_INJECT_POISON_LIMIT = 0x10, 117 CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11, 118 CXL_MBOX_ABORTED = 0x12, 119 CXL_MBOX_INVALID_SECURITY_STATE = 0x13, 120 CXL_MBOX_INCORRECT_PASSPHRASE = 0x14, 121 CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15, 122 CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16, 123 CXL_MBOX_INVALID_LOG = 0x17, 124 CXL_MBOX_INTERRUPTED = 0x18, 125 CXL_MBOX_UNSUPPORTED_FEATURE_VERSION = 0x19, 126 CXL_MBOX_UNSUPPORTED_FEATURE_SELECTION_VALUE = 0x1a, 127 CXL_MBOX_FEATURE_TRANSFER_IN_PROGRESS = 0x1b, 128 CXL_MBOX_FEATURE_TRANSFER_OUT_OF_ORDER = 0x1c, 129 CXL_MBOX_RESOURCES_EXHAUSTED = 0x1d, 130 CXL_MBOX_INVALID_EXTENT_LIST = 0x1e, 131 CXL_MBOX_TRANSFER_OUT_OF_ORDER = 0x1f, 132 CXL_MBOX_REQUEST_ABORT_NOTSUP = 0x20, 133 CXL_MBOX_MAX = 0x20 134 } CXLRetCode; 135 136 typedef struct CXLCCI CXLCCI; 137 typedef struct cxl_device_state CXLDeviceState; 138 struct cxl_cmd; 139 typedef CXLRetCode (*opcode_handler)(const struct cxl_cmd *cmd, 140 uint8_t *payload_in, size_t len_in, 141 uint8_t *payload_out, size_t *len_out, 142 CXLCCI *cci); 143 struct cxl_cmd { 144 const char *name; 145 opcode_handler handler; 146 ssize_t in; 147 uint16_t effect; /* Reported in CEL */ 148 }; 149 150 typedef struct CXLEvent { 151 CXLEventRecordRaw data; 152 QSIMPLEQ_ENTRY(CXLEvent) node; 153 } CXLEvent; 154 155 typedef struct CXLEventLog { 156 uint16_t next_handle; 157 uint16_t overflow_err_count; 158 uint64_t first_overflow_timestamp; 159 uint64_t last_overflow_timestamp; 160 bool irq_enabled; 161 int irq_vec; 162 QemuMutex lock; 163 QSIMPLEQ_HEAD(, CXLEvent) events; 164 } CXLEventLog; 165 166 typedef struct CXLCCI { 167 struct cxl_cmd cxl_cmd_set[256][256]; 168 struct cel_log { 169 uint16_t opcode; 170 uint16_t effect; 171 } cel_log[1 << 16]; 172 size_t cel_size; 173 174 /* background command handling (times in ms) */ 175 struct { 176 uint16_t opcode; 177 uint16_t complete_pct; 178 uint16_t ret_code; /* Current value of retcode */ 179 uint64_t starttime; 180 /* set by each bg cmd, cleared by the bg_timer when complete */ 181 uint64_t runtime; 182 QEMUTimer *timer; 183 } bg; 184 size_t payload_max; 185 /* Pointer to device hosting the CCI */ 186 DeviceState *d; 187 /* Pointer to the device hosting the protocol conversion */ 188 DeviceState *intf; 189 } CXLCCI; 190 191 typedef struct cxl_device_state { 192 MemoryRegion device_registers; 193 194 /* CXL r3.1 Section 8.2.8.3: Device Status Registers */ 195 struct { 196 MemoryRegion device; 197 union { 198 uint8_t dev_reg_state[CXL_DEVICE_STATUS_REGISTERS_LENGTH]; 199 uint16_t dev_reg_state16[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 2]; 200 uint32_t dev_reg_state32[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 4]; 201 uint64_t dev_reg_state64[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 8]; 202 }; 203 uint64_t event_status; 204 }; 205 MemoryRegion memory_device; 206 struct { 207 MemoryRegion caps; 208 union { 209 uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; 210 uint64_t caps_reg_state64[CXL_CAPS_SIZE / 8]; 211 }; 212 }; 213 214 /* CXL r3.1 Section 8.2.8.4: Mailbox Registers */ 215 struct { 216 MemoryRegion mailbox; 217 uint16_t payload_size; 218 uint8_t mbox_msi_n; 219 union { 220 uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH]; 221 uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2]; 222 uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4]; 223 uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8]; 224 }; 225 }; 226 227 /* Stash the memory device status value */ 228 uint64_t memdev_status; 229 230 struct { 231 bool set; 232 uint64_t last_set; 233 uint64_t host_set; 234 } timestamp; 235 236 /* memory region size, HDM */ 237 uint64_t static_mem_size; 238 uint64_t pmem_size; 239 uint64_t vmem_size; 240 241 const struct cxl_cmd (*cxl_cmd_set)[256]; 242 CXLEventLog event_logs[CXL_EVENT_TYPE_MAX]; 243 } CXLDeviceState; 244 245 /* Initialize the register block for a device */ 246 void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev, 247 CXLCCI *cci); 248 249 typedef struct CXLType3Dev CXLType3Dev; 250 typedef struct CSWMBCCIDev CSWMBCCIDev; 251 /* Set up default values for the register block */ 252 void cxl_device_register_init_t3(CXLType3Dev *ct3d); 253 void cxl_device_register_init_swcci(CSWMBCCIDev *sw); 254 255 /* 256 * CXL r3.1 Section 8.2.8.1: CXL Device Capabilities Array Register 257 * Documented as a 128 bit register, but 64 bit accesses and the second 258 * 64 bits are currently reserved. 259 */ 260 REG64(CXL_DEV_CAP_ARRAY, 0) 261 FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16) 262 FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8) 263 FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16) 264 265 void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type, 266 bool available); 267 268 /* 269 * Helper macro to initialize capability headers for CXL devices. 270 * 271 * In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is 272 * listed as a 128b register, but in CXL r3.1 Section 8.2.8: CXL Device Register 273 * Interface, it says: 274 * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that 275 * > is the maximum access size allowed for these registers. If this rule is not 276 * > followed, the behavior is undefined. 277 * 278 * > To illustrate how the fields fit together, the layouts ... are shown as 279 * > wider than a 64 bit register. Implementations are expected to use any size 280 * > accesses for this information up to 64 bits without lost of functionality 281 * 282 * Here we've chosen to make it 4 dwords. 283 */ 284 #define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \ 285 REG32(CXL_DEV_##n##_CAP_HDR0, offset) \ 286 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \ 287 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \ 288 REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \ 289 FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \ 290 REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \ 291 FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32) 292 293 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET) 294 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ 295 CXL_DEVICE_CAP_REG_SIZE) 296 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE, 297 CXL_DEVICE_CAP_HDR1_OFFSET + 298 CXL_DEVICE_CAP_REG_SIZE * 2) 299 300 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max); 301 void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf, 302 DeviceState *d, size_t payload_max); 303 void cxl_init_cci(CXLCCI *cci, size_t payload_max); 304 void cxl_add_cci_commands(CXLCCI *cci, const struct cxl_cmd (*cxl_cmd_set)[256], 305 size_t payload_max); 306 int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd, 307 size_t len_in, uint8_t *pl_in, 308 size_t *len_out, uint8_t *pl_out, 309 bool *bg_started); 310 void cxl_initialize_t3_fm_owned_ld_mctpcci(CXLCCI *cci, DeviceState *d, 311 DeviceState *intf, 312 size_t payload_max); 313 314 void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState *d, 315 DeviceState *intf, size_t payload_max); 316 317 #define cxl_device_cap_init(dstate, reg, cap_id, ver) \ 318 do { \ 319 uint32_t *cap_hdrs = dstate->caps_reg_state32; \ 320 int which = R_CXL_DEV_##reg##_CAP_HDR0; \ 321 cap_hdrs[which] = \ 322 FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, \ 323 CAP_ID, cap_id); \ 324 cap_hdrs[which] = FIELD_DP32( \ 325 cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, ver); \ 326 cap_hdrs[which + 1] = \ 327 FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \ 328 CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \ 329 cap_hdrs[which + 2] = \ 330 FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \ 331 CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \ 332 } while (0) 333 334 /* CXL r3.2 Section 8.2.8.3.1: Event Status Register */ 335 #define CXL_DEVICE_STATUS_VERSION 2 336 REG64(CXL_DEV_EVENT_STATUS, 0) 337 FIELD(CXL_DEV_EVENT_STATUS, EVENT_STATUS, 0, 32) 338 339 #define CXL_DEV_MAILBOX_VERSION 1 340 /* CXL r3.1 Section 8.2.8.4.3: Mailbox Capabilities Register */ 341 REG32(CXL_DEV_MAILBOX_CAP, 0) 342 FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) 343 FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) 344 FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1) 345 FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4) 346 FIELD(CXL_DEV_MAILBOX_CAP, MBOX_READY_TIME, 11, 8) 347 FIELD(CXL_DEV_MAILBOX_CAP, TYPE, 19, 4) 348 349 /* CXL r3.1 Section 8.2.8.4.4: Mailbox Control Register */ 350 REG32(CXL_DEV_MAILBOX_CTRL, 4) 351 FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1) 352 FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) 353 FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) 354 355 /* CXL r3.1 Section 8.2.8.4.5: Command Register */ 356 REG64(CXL_DEV_MAILBOX_CMD, 8) 357 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8) 358 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8) 359 FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20) 360 361 /* CXL r3.1 Section 8.2.8.4.6: Mailbox Status Register */ 362 REG64(CXL_DEV_MAILBOX_STS, 0x10) 363 FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1) 364 FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16) 365 FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16) 366 367 /* CXL r3.1 Section 8.2.8.4.7: Background Command Status Register */ 368 REG64(CXL_DEV_BG_CMD_STS, 0x18) 369 FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16) 370 FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7) 371 FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16) 372 FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16) 373 374 /* CXL r3.1 Section 8.2.8.4.8: Command Payload Registers */ 375 REG32(CXL_DEV_CMD_PAYLOAD, 0x20) 376 377 /* CXL r3.1 Section 8.2.8.4.1: Memory Device Status Registers */ 378 #define CXL_MEM_DEV_STATUS_VERSION 1 379 REG64(CXL_MEM_DEV_STS, 0) 380 FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1) 381 FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1) 382 FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2) 383 FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) 384 FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) 385 386 static inline void __toggle_media(CXLDeviceState *cxl_dstate, int val) 387 { 388 uint64_t dev_status_reg; 389 390 dev_status_reg = cxl_dstate->memdev_status; 391 dev_status_reg = FIELD_DP64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS, 392 val); 393 cxl_dstate->memdev_status = dev_status_reg; 394 } 395 #define cxl_dev_disable_media(cxlds) \ 396 do { __toggle_media((cxlds), 0x3); } while (0) 397 #define cxl_dev_enable_media(cxlds) \ 398 do { __toggle_media((cxlds), 0x1); } while (0) 399 400 static inline bool sanitize_running(CXLCCI *cci) 401 { 402 return !!cci->bg.runtime && cci->bg.opcode == 0x4400; 403 } 404 405 typedef struct CXLError { 406 QTAILQ_ENTRY(CXLError) node; 407 int type; /* Error code as per FE definition */ 408 uint32_t header[CXL_RAS_ERR_HEADER_NUM]; 409 } CXLError; 410 411 typedef QTAILQ_HEAD(, CXLError) CXLErrorList; 412 413 typedef struct CXLPoison { 414 uint64_t start, length; 415 uint8_t type; 416 #define CXL_POISON_TYPE_EXTERNAL 0x1 417 #define CXL_POISON_TYPE_INTERNAL 0x2 418 #define CXL_POISON_TYPE_INJECTED 0x3 419 QLIST_ENTRY(CXLPoison) node; 420 } CXLPoison; 421 422 typedef QLIST_HEAD(, CXLPoison) CXLPoisonList; 423 #define CXL_POISON_LIST_LIMIT 256 424 425 #define DCD_MAX_NUM_REGION 8 426 427 typedef struct CXLDCExtentRaw { 428 uint64_t start_dpa; 429 uint64_t len; 430 uint8_t tag[0x10]; 431 uint16_t shared_seq; 432 uint8_t rsvd[0x6]; 433 } QEMU_PACKED CXLDCExtentRaw; 434 435 typedef struct CXLDCExtent { 436 uint64_t start_dpa; 437 uint64_t len; 438 uint8_t tag[0x10]; 439 uint16_t shared_seq; 440 uint8_t rsvd[0x6]; 441 442 QTAILQ_ENTRY(CXLDCExtent) node; 443 } CXLDCExtent; 444 typedef QTAILQ_HEAD(, CXLDCExtent) CXLDCExtentList; 445 446 typedef struct CXLDCExtentGroup { 447 CXLDCExtentList list; 448 QTAILQ_ENTRY(CXLDCExtentGroup) node; 449 } CXLDCExtentGroup; 450 typedef QTAILQ_HEAD(, CXLDCExtentGroup) CXLDCExtentGroupList; 451 452 typedef struct CXLDCRegion { 453 uint64_t base; /* aligned to 256*MiB */ 454 uint64_t decode_len; /* aligned to 256*MiB */ 455 uint64_t len; 456 uint64_t block_size; 457 uint32_t dsmadhandle; 458 uint8_t flags; 459 } CXLDCRegion; 460 461 struct CXLType3Dev { 462 /* Private */ 463 PCIDevice parent_obj; 464 465 /* Properties */ 466 HostMemoryBackend *hostmem; /* deprecated */ 467 HostMemoryBackend *hostvmem; 468 HostMemoryBackend *hostpmem; 469 HostMemoryBackend *lsa; 470 uint64_t sn; 471 472 /* State */ 473 AddressSpace hostvmem_as; 474 AddressSpace hostpmem_as; 475 CXLComponentState cxl_cstate; 476 CXLDeviceState cxl_dstate; 477 CXLCCI cci; /* Primary PCI mailbox CCI */ 478 /* Always initialized as no way to know if a VDM might show up */ 479 CXLCCI vdm_fm_owned_ld_mctp_cci; 480 CXLCCI ld0_cci; 481 482 /* DOE */ 483 DOECap doe_cdat; 484 485 /* Error injection */ 486 CXLErrorList error_list; 487 488 /* Poison Injection - cache */ 489 CXLPoisonList poison_list; 490 unsigned int poison_list_cnt; 491 bool poison_list_overflowed; 492 uint64_t poison_list_overflow_ts; 493 494 struct dynamic_capacity { 495 HostMemoryBackend *host_dc; 496 AddressSpace host_dc_as; 497 /* 498 * total_capacity is equivalent to the dynamic capability 499 * memory region size. 500 */ 501 uint64_t total_capacity; /* 256M aligned */ 502 CXLDCExtentList extents; 503 CXLDCExtentGroupList extents_pending; 504 uint32_t total_extent_count; 505 uint32_t ext_list_gen_seq; 506 507 uint8_t num_regions; /* 0-8 regions */ 508 CXLDCRegion regions[DCD_MAX_NUM_REGION]; 509 } dc; 510 }; 511 512 #define TYPE_CXL_TYPE3 "cxl-type3" 513 OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3) 514 515 struct CXLType3Class { 516 /* Private */ 517 PCIDeviceClass parent_class; 518 519 /* public */ 520 uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); 521 522 uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size, 523 uint64_t offset); 524 void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size, 525 uint64_t offset); 526 bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset, 527 uint8_t *data); 528 }; 529 530 struct CSWMBCCIDev { 531 PCIDevice parent_obj; 532 PCIDevice *target; 533 CXLComponentState cxl_cstate; 534 CXLDeviceState cxl_dstate; 535 CXLCCI *cci; 536 }; 537 538 #define TYPE_CXL_SWITCH_MAILBOX_CCI "cxl-switch-mailbox-cci" 539 OBJECT_DECLARE_TYPE(CSWMBCCIDev, CSWMBCCIClass, CXL_SWITCH_MAILBOX_CCI) 540 541 MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, 542 unsigned size, MemTxAttrs attrs); 543 MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, 544 unsigned size, MemTxAttrs attrs); 545 546 uint64_t cxl_device_get_timestamp(CXLDeviceState *cxlds); 547 548 void cxl_event_init(CXLDeviceState *cxlds, int start_msg_num); 549 bool cxl_event_insert(CXLDeviceState *cxlds, CXLEventLogType log_type, 550 CXLEventRecordRaw *event); 551 CXLRetCode cxl_event_get_records(CXLDeviceState *cxlds, CXLGetEventPayload *pl, 552 uint8_t log_type, int max_recs, 553 size_t *len); 554 CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds, 555 CXLClearEventPayload *pl); 556 557 void cxl_event_irq_assert(CXLType3Dev *ct3d); 558 559 void cxl_set_poison_list_overflowed(CXLType3Dev *ct3d); 560 561 CXLDCRegion *cxl_find_dc_region(CXLType3Dev *ct3d, uint64_t dpa, uint64_t len); 562 563 void cxl_remove_extent_from_extent_list(CXLDCExtentList *list, 564 CXLDCExtent *extent); 565 void cxl_insert_extent_to_extent_list(CXLDCExtentList *list, uint64_t dpa, 566 uint64_t len, uint8_t *tag, 567 uint16_t shared_seq); 568 bool test_any_bits_set(const unsigned long *addr, unsigned long nr, 569 unsigned long size); 570 bool cxl_extents_contains_dpa_range(CXLDCExtentList *list, 571 uint64_t dpa, uint64_t len); 572 CXLDCExtentGroup *cxl_insert_extent_to_extent_group(CXLDCExtentGroup *group, 573 uint64_t dpa, 574 uint64_t len, 575 uint8_t *tag, 576 uint16_t shared_seq); 577 void cxl_extent_group_list_insert_tail(CXLDCExtentGroupList *list, 578 CXLDCExtentGroup *group); 579 void cxl_extent_group_list_delete_front(CXLDCExtentGroupList *list); 580 #endif 581