1 /* 2 * QEMU CXL Devices 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_DEVICE_H 11 #define CXL_DEVICE_H 12 13 #include "hw/cxl/cxl_component.h" 14 #include "hw/pci/pci_device.h" 15 #include "hw/register.h" 16 17 /* 18 * The following is how a CXL device's Memory Device registers are laid out. 19 * The only requirement from the spec is that the capabilities array and the 20 * capability headers start at offset 0 and are contiguously packed. The headers 21 * themselves provide offsets to the register fields. For this emulation, the 22 * actual registers * will start at offset 0x80 (m == 0x80). No secondary 23 * mailbox is implemented which means that the offset of the start of the 24 * mailbox payload (n) is given by 25 * n = m + sizeof(mailbox registers) + sizeof(device registers). 26 * 27 * +---------------------------------+ 28 * | | 29 * | Memory Device Registers | 30 * | | 31 * n + PAYLOAD_SIZE_MAX ----------------------------------- 32 * ^ | | 33 * | | | 34 * | | | 35 * | | | 36 * | | | 37 * | | Mailbox Payload | 38 * | | | 39 * | | | 40 * | | | 41 * n ----------------------------------- 42 * ^ | Mailbox Registers | 43 * | | | 44 * | ----------------------------------- 45 * | | | 46 * | | Device Registers | 47 * | | | 48 * m ----------------------------------> 49 * ^ | Memory Device Capability Header| 50 * | ----------------------------------- 51 * | | Mailbox Capability Header | 52 * | ----------------------------------- 53 * | | Device Capability Header | 54 * | ----------------------------------- 55 * | | Device Cap Array Register | 56 * 0 +---------------------------------+ 57 * 58 */ 59 60 #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10 /* Figure 138 */ 61 #define CXL_DEVICE_CAP_REG_SIZE 0x10 /* 8.2.8.2 */ 62 #define CXL_DEVICE_CAPS_MAX 4 /* 8.2.8.2.1 + 8.2.8.5 */ 63 #define CXL_CAPS_SIZE \ 64 (CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */ 65 66 #define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */ 67 #define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8 /* 8.2.8.3.1 */ 68 69 #define CXL_MAILBOX_REGISTERS_OFFSET \ 70 (CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH) 71 #define CXL_MAILBOX_REGISTERS_SIZE 0x20 /* 8.2.8.4, Figure 139 */ 72 #define CXL_MAILBOX_PAYLOAD_SHIFT 11 73 #define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT) 74 #define CXL_MAILBOX_REGISTERS_LENGTH \ 75 (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE) 76 77 #define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \ 78 (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH) 79 #define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8 80 81 #define CXL_MMIO_SIZE \ 82 (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH + \ 83 CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH) 84 85 typedef struct cxl_device_state { 86 MemoryRegion device_registers; 87 88 /* mmio for device capabilities array - 8.2.8.2 */ 89 MemoryRegion device; 90 MemoryRegion memory_device; 91 struct { 92 MemoryRegion caps; 93 union { 94 uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4]; 95 uint64_t caps_reg_state64[CXL_CAPS_SIZE / 8]; 96 }; 97 }; 98 99 /* mmio for the mailbox registers 8.2.8.4 */ 100 struct { 101 MemoryRegion mailbox; 102 uint16_t payload_size; 103 union { 104 uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH]; 105 uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2]; 106 uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4]; 107 uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8]; 108 }; 109 struct cel_log { 110 uint16_t opcode; 111 uint16_t effect; 112 } cel_log[1 << 16]; 113 size_t cel_size; 114 }; 115 116 struct { 117 bool set; 118 uint64_t last_set; 119 uint64_t host_set; 120 } timestamp; 121 122 /* memory region size, HDM */ 123 uint64_t mem_size; 124 uint64_t pmem_size; 125 uint64_t vmem_size; 126 } CXLDeviceState; 127 128 /* Initialize the register block for a device */ 129 void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev); 130 131 /* Set up default values for the register block */ 132 void cxl_device_register_init_common(CXLDeviceState *dev); 133 134 /* 135 * CXL 2.0 - 8.2.8.1 including errata F4 136 * Documented as a 128 bit register, but 64 bit accesses and the second 137 * 64 bits are currently reserved. 138 */ 139 REG64(CXL_DEV_CAP_ARRAY, 0) /* Documented as 128 bit register but 64 byte accesses */ 140 FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16) 141 FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8) 142 FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16) 143 144 /* 145 * Helper macro to initialize capability headers for CXL devices. 146 * 147 * In the 8.2.8.2, this is listed as a 128b register, but in 8.2.8, it says: 148 * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that 149 * > is the maximum access size allowed for these registers. If this rule is not 150 * > followed, the behavior is undefined 151 * 152 * CXL 2.0 Errata F4 states futher that the layouts in the specification are 153 * shown as greater than 128 bits, but implementations are expected to 154 * use any size of access up to 64 bits. 155 * 156 * Here we've chosen to make it 4 dwords. The spec allows any pow2 multiple 157 * access to be used for a register up to 64 bits. 158 */ 159 #define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset) \ 160 REG32(CXL_DEV_##n##_CAP_HDR0, offset) \ 161 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16) \ 162 FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \ 163 REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4) \ 164 FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32) \ 165 REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8) \ 166 FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32) 167 168 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET) 169 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \ 170 CXL_DEVICE_CAP_REG_SIZE) 171 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE, 172 CXL_DEVICE_CAP_HDR1_OFFSET + 173 CXL_DEVICE_CAP_REG_SIZE * 2) 174 175 void cxl_initialize_mailbox(CXLDeviceState *cxl_dstate); 176 void cxl_process_mailbox(CXLDeviceState *cxl_dstate); 177 178 #define cxl_device_cap_init(dstate, reg, cap_id) \ 179 do { \ 180 uint32_t *cap_hdrs = dstate->caps_reg_state32; \ 181 int which = R_CXL_DEV_##reg##_CAP_HDR0; \ 182 cap_hdrs[which] = \ 183 FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, \ 184 CAP_ID, cap_id); \ 185 cap_hdrs[which] = FIELD_DP32( \ 186 cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, 1); \ 187 cap_hdrs[which + 1] = \ 188 FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1, \ 189 CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET); \ 190 cap_hdrs[which + 2] = \ 191 FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2, \ 192 CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH); \ 193 } while (0) 194 195 /* CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register */ 196 REG32(CXL_DEV_MAILBOX_CAP, 0) 197 FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5) 198 FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1) 199 FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1) 200 FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4) 201 202 /* CXL 2.0 8.2.8.4.4 Mailbox Control Register */ 203 REG32(CXL_DEV_MAILBOX_CTRL, 4) 204 FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1) 205 FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1) 206 FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1) 207 208 /* CXL 2.0 8.2.8.4.5 Command Register */ 209 REG64(CXL_DEV_MAILBOX_CMD, 8) 210 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8) 211 FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8) 212 FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20) 213 214 /* CXL 2.0 8.2.8.4.6 Mailbox Status Register */ 215 REG64(CXL_DEV_MAILBOX_STS, 0x10) 216 FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1) 217 FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16) 218 FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16) 219 220 /* CXL 2.0 8.2.8.4.7 Background Command Status Register */ 221 REG64(CXL_DEV_BG_CMD_STS, 0x18) 222 FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16) 223 FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7) 224 FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16) 225 FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16) 226 227 /* CXL 2.0 8.2.8.4.8 Command Payload Registers */ 228 REG32(CXL_DEV_CMD_PAYLOAD, 0x20) 229 230 REG64(CXL_MEM_DEV_STS, 0) 231 FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1) 232 FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1) 233 FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2) 234 FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1) 235 FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3) 236 237 typedef struct CXLError { 238 QTAILQ_ENTRY(CXLError) node; 239 int type; /* Error code as per FE definition */ 240 uint32_t header[32]; 241 } CXLError; 242 243 typedef QTAILQ_HEAD(, CXLError) CXLErrorList; 244 245 struct CXLType3Dev { 246 /* Private */ 247 PCIDevice parent_obj; 248 249 /* Properties */ 250 HostMemoryBackend *hostmem; /* deprecated */ 251 HostMemoryBackend *hostvmem; 252 HostMemoryBackend *hostpmem; 253 HostMemoryBackend *lsa; 254 uint64_t sn; 255 256 /* State */ 257 AddressSpace hostvmem_as; 258 AddressSpace hostpmem_as; 259 CXLComponentState cxl_cstate; 260 CXLDeviceState cxl_dstate; 261 262 /* DOE */ 263 DOECap doe_cdat; 264 265 /* Error injection */ 266 CXLErrorList error_list; 267 }; 268 269 #define TYPE_CXL_TYPE3 "cxl-type3" 270 OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3) 271 272 struct CXLType3Class { 273 /* Private */ 274 PCIDeviceClass parent_class; 275 276 /* public */ 277 uint64_t (*get_lsa_size)(CXLType3Dev *ct3d); 278 279 uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size, 280 uint64_t offset); 281 void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size, 282 uint64_t offset); 283 }; 284 285 MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, 286 unsigned size, MemTxAttrs attrs); 287 MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, 288 unsigned size, MemTxAttrs attrs); 289 290 uint64_t cxl_device_get_timestamp(CXLDeviceState *cxlds); 291 292 #endif 293