xref: /openbmc/qemu/include/hw/cxl/cxl_device.h (revision 33a24910)
1 /*
2  * QEMU CXL Devices
3  *
4  * Copyright (c) 2020 Intel
5  *
6  * This work is licensed under the terms of the GNU GPL, version 2. See the
7  * COPYING file in the top-level directory.
8  */
9 
10 #ifndef CXL_DEVICE_H
11 #define CXL_DEVICE_H
12 
13 #include "hw/cxl/cxl_component.h"
14 #include "hw/pci/pci_device.h"
15 #include "hw/register.h"
16 #include "hw/cxl/cxl_events.h"
17 
18 /*
19  * The following is how a CXL device's Memory Device registers are laid out.
20  * The only requirement from the spec is that the capabilities array and the
21  * capability headers start at offset 0 and are contiguously packed. The headers
22  * themselves provide offsets to the register fields. For this emulation, the
23  * actual registers  * will start at offset 0x80 (m == 0x80). No secondary
24  * mailbox is implemented which means that the offset of the start of the
25  * mailbox payload (n) is given by
26  * n = m + sizeof(mailbox registers) + sizeof(device registers).
27  *
28  *                       +---------------------------------+
29  *                       |                                 |
30  *                       |    Memory Device Registers      |
31  *                       |                                 |
32  * n + PAYLOAD_SIZE_MAX  -----------------------------------
33  *                  ^    |                                 |
34  *                  |    |                                 |
35  *                  |    |                                 |
36  *                  |    |                                 |
37  *                  |    |                                 |
38  *                  |    |         Mailbox Payload         |
39  *                  |    |                                 |
40  *                  |    |                                 |
41  *                  |    |                                 |
42  *                  n    -----------------------------------
43  *                  ^    |       Mailbox Registers         |
44  *                  |    |                                 |
45  *                  |    -----------------------------------
46  *                  |    |                                 |
47  *                  |    |        Device Registers         |
48  *                  |    |                                 |
49  *                  m    ---------------------------------->
50  *                  ^    |  Memory Device Capability Header|
51  *                  |    -----------------------------------
52  *                  |    |     Mailbox Capability Header   |
53  *                  |    -----------------------------------
54  *                  |    |     Device Capability Header    |
55  *                  |    -----------------------------------
56  *                  |    |     Device Cap Array Register   |
57  *                  0    +---------------------------------+
58  *
59  */
60 
61 /* CXL r3.1 Figure 8-12: CXL Device Registers */
62 #define CXL_DEVICE_CAP_HDR1_OFFSET 0x10
63 /* CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register */
64 #define CXL_DEVICE_CAP_REG_SIZE 0x10
65 
66 /*
67  * CXL r3.1 Section 8.2.8.2.1: CXL Device Capabilities +
68  * CXL r3.1 Section 8.2.8.5: Memory Device Capabilities
69  */
70 #define CXL_DEVICE_CAPS_MAX 4
71 #define CXL_CAPS_SIZE \
72     (CXL_DEVICE_CAP_REG_SIZE * (CXL_DEVICE_CAPS_MAX + 1)) /* +1 for header */
73 
74 #define CXL_DEVICE_STATUS_REGISTERS_OFFSET 0x80 /* Read comment above */
75 /*
76  * CXL r3.1 Section 8.2.8.3: Device Status Registers
77  * As it is the only Device Status Register in CXL r3.1
78  */
79 #define CXL_DEVICE_STATUS_REGISTERS_LENGTH 0x8
80 
81 #define CXL_MAILBOX_REGISTERS_OFFSET \
82     (CXL_DEVICE_STATUS_REGISTERS_OFFSET + CXL_DEVICE_STATUS_REGISTERS_LENGTH)
83 /* CXL r3.1 Figure 8-13: Mailbox Registers */
84 #define CXL_MAILBOX_REGISTERS_SIZE 0x20
85 #define CXL_MAILBOX_PAYLOAD_SHIFT 11
86 #define CXL_MAILBOX_MAX_PAYLOAD_SIZE (1 << CXL_MAILBOX_PAYLOAD_SHIFT)
87 #define CXL_MAILBOX_REGISTERS_LENGTH \
88     (CXL_MAILBOX_REGISTERS_SIZE + CXL_MAILBOX_MAX_PAYLOAD_SIZE)
89 
90 #define CXL_MEMORY_DEVICE_REGISTERS_OFFSET \
91     (CXL_MAILBOX_REGISTERS_OFFSET + CXL_MAILBOX_REGISTERS_LENGTH)
92 #define CXL_MEMORY_DEVICE_REGISTERS_LENGTH 0x8
93 
94 #define CXL_MMIO_SIZE                                                   \
95     (CXL_DEVICE_CAP_REG_SIZE + CXL_DEVICE_STATUS_REGISTERS_LENGTH +     \
96      CXL_MAILBOX_REGISTERS_LENGTH + CXL_MEMORY_DEVICE_REGISTERS_LENGTH)
97 
98 /* CXL r3.1 Table 8-34: Command Return Codes */
99 typedef enum {
100     CXL_MBOX_SUCCESS = 0x0,
101     CXL_MBOX_BG_STARTED = 0x1,
102     CXL_MBOX_INVALID_INPUT = 0x2,
103     CXL_MBOX_UNSUPPORTED = 0x3,
104     CXL_MBOX_INTERNAL_ERROR = 0x4,
105     CXL_MBOX_RETRY_REQUIRED = 0x5,
106     CXL_MBOX_BUSY = 0x6,
107     CXL_MBOX_MEDIA_DISABLED = 0x7,
108     CXL_MBOX_FW_XFER_IN_PROGRESS = 0x8,
109     CXL_MBOX_FW_XFER_OUT_OF_ORDER = 0x9,
110     CXL_MBOX_FW_AUTH_FAILED = 0xa,
111     CXL_MBOX_FW_INVALID_SLOT = 0xb,
112     CXL_MBOX_FW_ROLLEDBACK = 0xc,
113     CXL_MBOX_FW_REST_REQD = 0xd,
114     CXL_MBOX_INVALID_HANDLE = 0xe,
115     CXL_MBOX_INVALID_PA = 0xf,
116     CXL_MBOX_INJECT_POISON_LIMIT = 0x10,
117     CXL_MBOX_PERMANENT_MEDIA_FAILURE = 0x11,
118     CXL_MBOX_ABORTED = 0x12,
119     CXL_MBOX_INVALID_SECURITY_STATE = 0x13,
120     CXL_MBOX_INCORRECT_PASSPHRASE = 0x14,
121     CXL_MBOX_UNSUPPORTED_MAILBOX = 0x15,
122     CXL_MBOX_INVALID_PAYLOAD_LENGTH = 0x16,
123     CXL_MBOX_INVALID_LOG = 0x17,
124     CXL_MBOX_INTERRUPTED = 0x18,
125     CXL_MBOX_UNSUPPORTED_FEATURE_VERSION = 0x19,
126     CXL_MBOX_UNSUPPORTED_FEATURE_SELECTION_VALUE = 0x1a,
127     CXL_MBOX_FEATURE_TRANSFER_IN_PROGRESS = 0x1b,
128     CXL_MBOX_FEATURE_TRANSFER_OUT_OF_ORDER = 0x1c,
129     CXL_MBOX_RESOURCES_EXHAUSTED = 0x1d,
130     CXL_MBOX_INVALID_EXTENT_LIST = 0x1e,
131     CXL_MBOX_TRANSFER_OUT_OF_ORDER = 0x1f,
132     CXL_MBOX_REQUEST_ABORT_NOTSUP = 0x20,
133     CXL_MBOX_MAX = 0x20
134 } CXLRetCode;
135 
136 typedef struct CXLCCI CXLCCI;
137 typedef struct cxl_device_state CXLDeviceState;
138 struct cxl_cmd;
139 typedef CXLRetCode (*opcode_handler)(const struct cxl_cmd *cmd,
140                                      uint8_t *payload_in, size_t len_in,
141                                      uint8_t *payload_out, size_t *len_out,
142                                      CXLCCI *cci);
143 struct cxl_cmd {
144     const char *name;
145     opcode_handler handler;
146     ssize_t in;
147     uint16_t effect; /* Reported in CEL */
148 };
149 
150 typedef struct CXLEvent {
151     CXLEventRecordRaw data;
152     QSIMPLEQ_ENTRY(CXLEvent) node;
153 } CXLEvent;
154 
155 typedef struct CXLEventLog {
156     uint16_t next_handle;
157     uint16_t overflow_err_count;
158     uint64_t first_overflow_timestamp;
159     uint64_t last_overflow_timestamp;
160     bool irq_enabled;
161     int irq_vec;
162     QemuMutex lock;
163     QSIMPLEQ_HEAD(, CXLEvent) events;
164 } CXLEventLog;
165 
166 typedef struct CXLCCI {
167     const struct cxl_cmd (*cxl_cmd_set)[256];
168     struct cel_log {
169         uint16_t opcode;
170         uint16_t effect;
171     } cel_log[1 << 16];
172     size_t cel_size;
173 
174     /* background command handling (times in ms) */
175     struct {
176         uint16_t opcode;
177         uint16_t complete_pct;
178         uint16_t ret_code; /* Current value of retcode */
179         uint64_t starttime;
180         /* set by each bg cmd, cleared by the bg_timer when complete */
181         uint64_t runtime;
182         QEMUTimer *timer;
183     } bg;
184     size_t payload_max;
185     /* Pointer to device hosting the CCI */
186     DeviceState *d;
187     /* Pointer to the device hosting the protocol conversion */
188     DeviceState *intf;
189 } CXLCCI;
190 
191 typedef struct cxl_device_state {
192     MemoryRegion device_registers;
193 
194     /* CXL r3.1 Section 8.2.8.3: Device Status Registers */
195     struct {
196         MemoryRegion device;
197         union {
198             uint8_t dev_reg_state[CXL_DEVICE_STATUS_REGISTERS_LENGTH];
199             uint16_t dev_reg_state16[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 2];
200             uint32_t dev_reg_state32[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 4];
201             uint64_t dev_reg_state64[CXL_DEVICE_STATUS_REGISTERS_LENGTH / 8];
202         };
203         uint64_t event_status;
204     };
205     MemoryRegion memory_device;
206     struct {
207         MemoryRegion caps;
208         union {
209             uint32_t caps_reg_state32[CXL_CAPS_SIZE / 4];
210             uint64_t caps_reg_state64[CXL_CAPS_SIZE / 8];
211         };
212     };
213 
214     /* CXL r3.1 Section 8.2.8.4: Mailbox Registers */
215     struct {
216         MemoryRegion mailbox;
217         uint16_t payload_size;
218         uint8_t mbox_msi_n;
219         union {
220             uint8_t mbox_reg_state[CXL_MAILBOX_REGISTERS_LENGTH];
221             uint16_t mbox_reg_state16[CXL_MAILBOX_REGISTERS_LENGTH / 2];
222             uint32_t mbox_reg_state32[CXL_MAILBOX_REGISTERS_LENGTH / 4];
223             uint64_t mbox_reg_state64[CXL_MAILBOX_REGISTERS_LENGTH / 8];
224         };
225     };
226 
227     /* Stash the memory device status value */
228     uint64_t memdev_status;
229 
230     struct {
231         bool set;
232         uint64_t last_set;
233         uint64_t host_set;
234     } timestamp;
235 
236     /* memory region size, HDM */
237     uint64_t mem_size;
238     uint64_t pmem_size;
239     uint64_t vmem_size;
240 
241     const struct cxl_cmd (*cxl_cmd_set)[256];
242     CXLEventLog event_logs[CXL_EVENT_TYPE_MAX];
243 } CXLDeviceState;
244 
245 /* Initialize the register block for a device */
246 void cxl_device_register_block_init(Object *obj, CXLDeviceState *dev,
247                                     CXLCCI *cci);
248 
249 typedef struct CXLType3Dev CXLType3Dev;
250 typedef struct CSWMBCCIDev CSWMBCCIDev;
251 /* Set up default values for the register block */
252 void cxl_device_register_init_t3(CXLType3Dev *ct3d);
253 void cxl_device_register_init_swcci(CSWMBCCIDev *sw);
254 
255 /*
256  * CXL r3.1 Section 8.2.8.1: CXL Device Capabilities Array Register
257  * Documented as a 128 bit register, but 64 bit accesses and the second
258  * 64 bits are currently reserved.
259  */
260 REG64(CXL_DEV_CAP_ARRAY, 0)
261     FIELD(CXL_DEV_CAP_ARRAY, CAP_ID, 0, 16)
262     FIELD(CXL_DEV_CAP_ARRAY, CAP_VERSION, 16, 8)
263     FIELD(CXL_DEV_CAP_ARRAY, CAP_COUNT, 32, 16)
264 
265 void cxl_event_set_status(CXLDeviceState *cxl_dstate, CXLEventLogType log_type,
266                           bool available);
267 
268 /*
269  * Helper macro to initialize capability headers for CXL devices.
270  *
271  * In CXL r3.1 Section 8.2.8.2: CXL Device Capability Header Register, this is
272  * listed as a 128b register, but in CXL r3.1 Section 8.2.8: CXL Device Register
273  * Interface, it says:
274  * > No registers defined in Section 8.2.8 are larger than 64-bits wide so that
275  * > is the maximum access size allowed for these registers. If this rule is not
276  * > followed, the behavior is undefined.
277  *
278  * > To illustrate how the fields fit together, the layouts ... are shown as
279  * > wider than a 64 bit register. Implementations are expected to use any size
280  * > accesses for this information up to 64 bits without lost of functionality
281  *
282  * Here we've chosen to make it 4 dwords.
283  */
284 #define CXL_DEVICE_CAPABILITY_HEADER_REGISTER(n, offset)  \
285     REG32(CXL_DEV_##n##_CAP_HDR0, offset)                 \
286         FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_ID, 0, 16)      \
287         FIELD(CXL_DEV_##n##_CAP_HDR0, CAP_VERSION, 16, 8) \
288     REG32(CXL_DEV_##n##_CAP_HDR1, offset + 4)             \
289         FIELD(CXL_DEV_##n##_CAP_HDR1, CAP_OFFSET, 0, 32)  \
290     REG32(CXL_DEV_##n##_CAP_HDR2, offset + 8)             \
291         FIELD(CXL_DEV_##n##_CAP_HDR2, CAP_LENGTH, 0, 32)
292 
293 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(DEVICE_STATUS, CXL_DEVICE_CAP_HDR1_OFFSET)
294 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MAILBOX, CXL_DEVICE_CAP_HDR1_OFFSET + \
295                                                CXL_DEVICE_CAP_REG_SIZE)
296 CXL_DEVICE_CAPABILITY_HEADER_REGISTER(MEMORY_DEVICE,
297                                       CXL_DEVICE_CAP_HDR1_OFFSET +
298                                           CXL_DEVICE_CAP_REG_SIZE * 2)
299 
300 void cxl_initialize_mailbox_t3(CXLCCI *cci, DeviceState *d, size_t payload_max);
301 void cxl_initialize_mailbox_swcci(CXLCCI *cci, DeviceState *intf,
302                                   DeviceState *d, size_t payload_max);
303 void cxl_init_cci(CXLCCI *cci, size_t payload_max);
304 int cxl_process_cci_message(CXLCCI *cci, uint8_t set, uint8_t cmd,
305                             size_t len_in, uint8_t *pl_in,
306                             size_t *len_out, uint8_t *pl_out,
307                             bool *bg_started);
308 void cxl_initialize_t3_fm_owned_ld_mctpcci(CXLCCI *cci, DeviceState *d,
309                                            DeviceState *intf,
310                                            size_t payload_max);
311 
312 void cxl_initialize_t3_ld_cci(CXLCCI *cci, DeviceState *d,
313                               DeviceState *intf, size_t payload_max);
314 
315 #define cxl_device_cap_init(dstate, reg, cap_id, ver)                      \
316     do {                                                                   \
317         uint32_t *cap_hdrs = dstate->caps_reg_state32;                     \
318         int which = R_CXL_DEV_##reg##_CAP_HDR0;                            \
319         cap_hdrs[which] =                                                  \
320             FIELD_DP32(cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0,          \
321                        CAP_ID, cap_id);                                    \
322         cap_hdrs[which] = FIELD_DP32(                                      \
323             cap_hdrs[which], CXL_DEV_##reg##_CAP_HDR0, CAP_VERSION, ver);  \
324         cap_hdrs[which + 1] =                                              \
325             FIELD_DP32(cap_hdrs[which + 1], CXL_DEV_##reg##_CAP_HDR1,      \
326                        CAP_OFFSET, CXL_##reg##_REGISTERS_OFFSET);          \
327         cap_hdrs[which + 2] =                                              \
328             FIELD_DP32(cap_hdrs[which + 2], CXL_DEV_##reg##_CAP_HDR2,      \
329                        CAP_LENGTH, CXL_##reg##_REGISTERS_LENGTH);          \
330     } while (0)
331 
332 /* CXL r3.2 Section 8.2.8.3.1: Event Status Register */
333 #define CXL_DEVICE_STATUS_VERSION 2
334 REG64(CXL_DEV_EVENT_STATUS, 0)
335     FIELD(CXL_DEV_EVENT_STATUS, EVENT_STATUS, 0, 32)
336 
337 #define CXL_DEV_MAILBOX_VERSION 1
338 /* CXL r3.1 Section 8.2.8.4.3: Mailbox Capabilities Register */
339 REG32(CXL_DEV_MAILBOX_CAP, 0)
340     FIELD(CXL_DEV_MAILBOX_CAP, PAYLOAD_SIZE, 0, 5)
341     FIELD(CXL_DEV_MAILBOX_CAP, INT_CAP, 5, 1)
342     FIELD(CXL_DEV_MAILBOX_CAP, BG_INT_CAP, 6, 1)
343     FIELD(CXL_DEV_MAILBOX_CAP, MSI_N, 7, 4)
344     FIELD(CXL_DEV_MAILBOX_CAP, MBOX_READY_TIME, 11, 8)
345     FIELD(CXL_DEV_MAILBOX_CAP, TYPE, 19, 4)
346 
347 /* CXL r3.1 Section 8.2.8.4.4: Mailbox Control Register */
348 REG32(CXL_DEV_MAILBOX_CTRL, 4)
349     FIELD(CXL_DEV_MAILBOX_CTRL, DOORBELL, 0, 1)
350     FIELD(CXL_DEV_MAILBOX_CTRL, INT_EN, 1, 1)
351     FIELD(CXL_DEV_MAILBOX_CTRL, BG_INT_EN, 2, 1)
352 
353 /* CXL r3.1 Section 8.2.8.4.5: Command Register */
354 REG64(CXL_DEV_MAILBOX_CMD, 8)
355     FIELD(CXL_DEV_MAILBOX_CMD, COMMAND, 0, 8)
356     FIELD(CXL_DEV_MAILBOX_CMD, COMMAND_SET, 8, 8)
357     FIELD(CXL_DEV_MAILBOX_CMD, LENGTH, 16, 20)
358 
359 /* CXL r3.1 Section 8.2.8.4.6: Mailbox Status Register */
360 REG64(CXL_DEV_MAILBOX_STS, 0x10)
361     FIELD(CXL_DEV_MAILBOX_STS, BG_OP, 0, 1)
362     FIELD(CXL_DEV_MAILBOX_STS, ERRNO, 32, 16)
363     FIELD(CXL_DEV_MAILBOX_STS, VENDOR_ERRNO, 48, 16)
364 
365 /* CXL r3.1 Section 8.2.8.4.7: Background Command Status Register */
366 REG64(CXL_DEV_BG_CMD_STS, 0x18)
367     FIELD(CXL_DEV_BG_CMD_STS, OP, 0, 16)
368     FIELD(CXL_DEV_BG_CMD_STS, PERCENTAGE_COMP, 16, 7)
369     FIELD(CXL_DEV_BG_CMD_STS, RET_CODE, 32, 16)
370     FIELD(CXL_DEV_BG_CMD_STS, VENDOR_RET_CODE, 48, 16)
371 
372 /* CXL r3.1 Section 8.2.8.4.8: Command Payload Registers */
373 REG32(CXL_DEV_CMD_PAYLOAD, 0x20)
374 
375 /* CXL r3.1 Section 8.2.8.4.1: Memory Device Status Registers */
376 #define CXL_MEM_DEV_STATUS_VERSION 1
377 REG64(CXL_MEM_DEV_STS, 0)
378     FIELD(CXL_MEM_DEV_STS, FATAL, 0, 1)
379     FIELD(CXL_MEM_DEV_STS, FW_HALT, 1, 1)
380     FIELD(CXL_MEM_DEV_STS, MEDIA_STATUS, 2, 2)
381     FIELD(CXL_MEM_DEV_STS, MBOX_READY, 4, 1)
382     FIELD(CXL_MEM_DEV_STS, RESET_NEEDED, 5, 3)
383 
384 static inline void __toggle_media(CXLDeviceState *cxl_dstate, int val)
385 {
386     uint64_t dev_status_reg;
387 
388     dev_status_reg = cxl_dstate->memdev_status;
389     dev_status_reg = FIELD_DP64(dev_status_reg, CXL_MEM_DEV_STS, MEDIA_STATUS,
390                                 val);
391     cxl_dstate->memdev_status = dev_status_reg;
392 }
393 #define cxl_dev_disable_media(cxlds)                    \
394         do { __toggle_media((cxlds), 0x3); } while (0)
395 #define cxl_dev_enable_media(cxlds)                     \
396         do { __toggle_media((cxlds), 0x1); } while (0)
397 
398 static inline bool sanitize_running(CXLCCI *cci)
399 {
400     return !!cci->bg.runtime && cci->bg.opcode == 0x4400;
401 }
402 
403 typedef struct CXLError {
404     QTAILQ_ENTRY(CXLError) node;
405     int type; /* Error code as per FE definition */
406     uint32_t header[CXL_RAS_ERR_HEADER_NUM];
407 } CXLError;
408 
409 typedef QTAILQ_HEAD(, CXLError) CXLErrorList;
410 
411 typedef struct CXLPoison {
412     uint64_t start, length;
413     uint8_t type;
414 #define CXL_POISON_TYPE_EXTERNAL 0x1
415 #define CXL_POISON_TYPE_INTERNAL 0x2
416 #define CXL_POISON_TYPE_INJECTED 0x3
417     QLIST_ENTRY(CXLPoison) node;
418 } CXLPoison;
419 
420 typedef QLIST_HEAD(, CXLPoison) CXLPoisonList;
421 #define CXL_POISON_LIST_LIMIT 256
422 
423 struct CXLType3Dev {
424     /* Private */
425     PCIDevice parent_obj;
426 
427     /* Properties */
428     HostMemoryBackend *hostmem; /* deprecated */
429     HostMemoryBackend *hostvmem;
430     HostMemoryBackend *hostpmem;
431     HostMemoryBackend *lsa;
432     uint64_t sn;
433 
434     /* State */
435     AddressSpace hostvmem_as;
436     AddressSpace hostpmem_as;
437     CXLComponentState cxl_cstate;
438     CXLDeviceState cxl_dstate;
439     CXLCCI cci; /* Primary PCI mailbox CCI */
440     /* Always initialized as no way to know if a VDM might show up */
441     CXLCCI vdm_fm_owned_ld_mctp_cci;
442     CXLCCI ld0_cci;
443 
444     /* DOE */
445     DOECap doe_cdat;
446 
447     /* Error injection */
448     CXLErrorList error_list;
449 
450     /* Poison Injection - cache */
451     CXLPoisonList poison_list;
452     unsigned int poison_list_cnt;
453     bool poison_list_overflowed;
454     uint64_t poison_list_overflow_ts;
455 };
456 
457 #define TYPE_CXL_TYPE3 "cxl-type3"
458 OBJECT_DECLARE_TYPE(CXLType3Dev, CXLType3Class, CXL_TYPE3)
459 
460 struct CXLType3Class {
461     /* Private */
462     PCIDeviceClass parent_class;
463 
464     /* public */
465     uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
466 
467     uint64_t (*get_lsa)(CXLType3Dev *ct3d, void *buf, uint64_t size,
468                         uint64_t offset);
469     void (*set_lsa)(CXLType3Dev *ct3d, const void *buf, uint64_t size,
470                     uint64_t offset);
471     bool (*set_cacheline)(CXLType3Dev *ct3d, uint64_t dpa_offset,
472                           uint8_t *data);
473 };
474 
475 struct CSWMBCCIDev {
476     PCIDevice parent_obj;
477     PCIDevice *target;
478     CXLComponentState cxl_cstate;
479     CXLDeviceState cxl_dstate;
480     CXLCCI *cci;
481 };
482 
483 #define TYPE_CXL_SWITCH_MAILBOX_CCI "cxl-switch-mailbox-cci"
484 OBJECT_DECLARE_TYPE(CSWMBCCIDev, CSWMBCCIClass, CXL_SWITCH_MAILBOX_CCI)
485 
486 MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data,
487                            unsigned size, MemTxAttrs attrs);
488 MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data,
489                             unsigned size, MemTxAttrs attrs);
490 
491 uint64_t cxl_device_get_timestamp(CXLDeviceState *cxlds);
492 
493 void cxl_event_init(CXLDeviceState *cxlds, int start_msg_num);
494 bool cxl_event_insert(CXLDeviceState *cxlds, CXLEventLogType log_type,
495                       CXLEventRecordRaw *event);
496 CXLRetCode cxl_event_get_records(CXLDeviceState *cxlds, CXLGetEventPayload *pl,
497                                  uint8_t log_type, int max_recs,
498                                  size_t *len);
499 CXLRetCode cxl_event_clear_records(CXLDeviceState *cxlds,
500                                    CXLClearEventPayload *pl);
501 
502 void cxl_event_irq_assert(CXLType3Dev *ct3d);
503 
504 void cxl_set_poison_list_overflowed(CXLType3Dev *ct3d);
505 
506 #endif
507