1 /* 2 * QEMU CXL Component 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_COMPONENT_H 11 #define CXL_COMPONENT_H 12 13 /* CXL 2.0 - 8.2.4 */ 14 #define CXL2_COMPONENT_IO_REGION_SIZE 0x1000 15 #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000 16 #define CXL2_COMPONENT_BLOCK_SIZE 0x10000 17 18 #include "qemu/compiler.h" 19 #include "qemu/range.h" 20 #include "qemu/typedefs.h" 21 #include "hw/register.h" 22 23 enum reg_type { 24 CXL2_DEVICE, 25 CXL2_TYPE3_DEVICE, 26 CXL2_LOGICAL_DEVICE, 27 CXL2_ROOT_PORT, 28 CXL2_UPSTREAM_PORT, 29 CXL2_DOWNSTREAM_PORT 30 }; 31 32 /* 33 * Capability registers are defined at the top of the CXL.cache/mem region and 34 * are packed. For our purposes we will always define the caps in the same 35 * order. 36 * CXL 2.0 - 8.2.5 Table 142 for details. 37 */ 38 39 /* CXL 2.0 - 8.2.5.1 */ 40 REG32(CXL_CAPABILITY_HEADER, 0) 41 FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16) 42 FIELD(CXL_CAPABILITY_HEADER, VERSION, 16, 4) 43 FIELD(CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 20, 4) 44 FIELD(CXL_CAPABILITY_HEADER, ARRAY_SIZE, 24, 8) 45 46 #define CXLx_CAPABILITY_HEADER(type, offset) \ 47 REG32(CXL_##type##_CAPABILITY_HEADER, offset) \ 48 FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \ 49 FIELD(CXL_##type##_CAPABILITY_HEADER, VERSION, 16, 4) \ 50 FIELD(CXL_##type##_CAPABILITY_HEADER, PTR, 20, 12) 51 CXLx_CAPABILITY_HEADER(RAS, 0x4) 52 CXLx_CAPABILITY_HEADER(LINK, 0x8) 53 CXLx_CAPABILITY_HEADER(HDM, 0xc) 54 CXLx_CAPABILITY_HEADER(EXTSEC, 0x10) 55 CXLx_CAPABILITY_HEADER(SNOOP, 0x14) 56 57 /* 58 * Capability structures contain the actual registers that the CXL component 59 * implements. Some of these are specific to certain types of components, but 60 * this implementation leaves enough space regardless. 61 */ 62 /* 8.2.5.9 - CXL RAS Capability Structure */ 63 64 /* Give ample space for caps before this */ 65 #define CXL_RAS_REGISTERS_OFFSET 0x80 66 #define CXL_RAS_REGISTERS_SIZE 0x58 67 REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET) 68 REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4) 69 REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8) 70 REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc) 71 REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10) 72 REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14) 73 /* Offset 0x18 - 0x58 reserved for RAS logs */ 74 75 /* 8.2.5.10 - CXL Security Capability Structure */ 76 #define CXL_SEC_REGISTERS_OFFSET \ 77 (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE) 78 #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */ 79 80 /* 8.2.5.11 - CXL Link Capability Structure */ 81 #define CXL_LINK_REGISTERS_OFFSET \ 82 (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE) 83 #define CXL_LINK_REGISTERS_SIZE 0x38 84 85 /* 8.2.5.12 - CXL HDM Decoder Capability Structure */ 86 #define HDM_DECODE_MAX 10 /* 8.2.5.12.1 */ 87 #define CXL_HDM_REGISTERS_OFFSET \ 88 (CXL_LINK_REGISTERS_OFFSET + CXL_LINK_REGISTERS_SIZE) 89 #define CXL_HDM_REGISTERS_SIZE (0x10 + 0x20 * HDM_DECODE_MAX) 90 #define HDM_DECODER_INIT(n) \ 91 REG32(CXL_HDM_DECODER##n##_BASE_LO, \ 92 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) \ 93 FIELD(CXL_HDM_DECODER##n##_BASE_LO, L, 28, 4) \ 94 REG32(CXL_HDM_DECODER##n##_BASE_HI, \ 95 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) \ 96 REG32(CXL_HDM_DECODER##n##_SIZE_LO, \ 97 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) \ 98 REG32(CXL_HDM_DECODER##n##_SIZE_HI, \ 99 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) \ 100 REG32(CXL_HDM_DECODER##n##_CTRL, \ 101 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x20) \ 102 FIELD(CXL_HDM_DECODER##n##_CTRL, IG, 0, 4) \ 103 FIELD(CXL_HDM_DECODER##n##_CTRL, IW, 4, 4) \ 104 FIELD(CXL_HDM_DECODER##n##_CTRL, LOCK_ON_COMMIT, 8, 1) \ 105 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMIT, 9, 1) \ 106 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMITTED, 10, 1) \ 107 FIELD(CXL_HDM_DECODER##n##_CTRL, ERR, 11, 1) \ 108 FIELD(CXL_HDM_DECODER##n##_CTRL, TYPE, 12, 1) \ 109 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_LO, \ 110 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ 111 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_HI, \ 112 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) 113 114 REG32(CXL_HDM_DECODER_CAPABILITY, CXL_HDM_REGISTERS_OFFSET) 115 FIELD(CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 0, 4) 116 FIELD(CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 4, 4) 117 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 8, 1) 118 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 9, 1) 119 FIELD(CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 10, 1) 120 REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4) 121 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1) 122 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1) 123 124 HDM_DECODER_INIT(0); 125 126 /* 8.2.5.13 - CXL Extended Security Capability Structure (Root complex only) */ 127 #define EXTSEC_ENTRY_MAX 256 128 #define CXL_EXTSEC_REGISTERS_OFFSET \ 129 (CXL_HDM_REGISTERS_OFFSET + CXL_HDM_REGISTERS_SIZE) 130 #define CXL_EXTSEC_REGISTERS_SIZE (8 * EXTSEC_ENTRY_MAX + 4) 131 132 /* 8.2.5.14 - CXL IDE Capability Structure */ 133 #define CXL_IDE_REGISTERS_OFFSET \ 134 (CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC_REGISTERS_SIZE) 135 #define CXL_IDE_REGISTERS_SIZE 0x20 136 137 /* 8.2.5.15 - CXL Snoop Filter Capability Structure */ 138 #define CXL_SNOOP_REGISTERS_OFFSET \ 139 (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE) 140 #define CXL_SNOOP_REGISTERS_SIZE 0x8 141 142 QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) >= 0x1000, 143 "No space for registers"); 144 145 typedef struct component_registers { 146 /* 147 * Main memory region to be registered with QEMU core. 148 */ 149 MemoryRegion component_registers; 150 151 /* 152 * 8.2.4 Table 141: 153 * 0x0000 - 0x0fff CXL.io registers 154 * 0x1000 - 0x1fff CXL.cache and CXL.mem 155 * 0x2000 - 0xdfff Implementation specific 156 * 0xe000 - 0xe3ff CXL ARB/MUX registers 157 * 0xe400 - 0xffff RSVD 158 */ 159 uint32_t io_registers[CXL2_COMPONENT_IO_REGION_SIZE >> 2]; 160 MemoryRegion io; 161 162 uint32_t cache_mem_registers[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 163 uint32_t cache_mem_regs_write_mask[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 164 MemoryRegion cache_mem; 165 166 MemoryRegion impl_specific; 167 MemoryRegion arb_mux; 168 MemoryRegion rsvd; 169 170 /* special_ops is used for any component that needs any specific handling */ 171 MemoryRegionOps *special_ops; 172 } ComponentRegisters; 173 174 /* 175 * A CXL component represents all entities in a CXL hierarchy. This includes, 176 * host bridges, root ports, upstream/downstream switch ports, and devices 177 */ 178 typedef struct cxl_component { 179 ComponentRegisters crb; 180 union { 181 struct { 182 Range dvsecs[CXL20_MAX_DVSEC]; 183 uint16_t dvsec_offset; 184 struct PCIDevice *pdev; 185 }; 186 }; 187 } CXLComponentState; 188 189 void cxl_component_register_block_init(Object *obj, 190 CXLComponentState *cxl_cstate, 191 const char *type); 192 void cxl_component_register_init_common(uint32_t *reg_state, 193 uint32_t *write_msk, 194 enum reg_type type); 195 196 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, 197 enum reg_type cxl_dev_type, uint16_t length, 198 uint16_t type, uint8_t rev, uint8_t *body); 199 200 static inline int cxl_decoder_count_enc(int count) 201 { 202 switch (count) { 203 case 1: return 0; 204 case 2: return 1; 205 case 4: return 2; 206 case 6: return 3; 207 case 8: return 4; 208 case 10: return 5; 209 } 210 return 0; 211 } 212 213 uint8_t cxl_interleave_ways_enc(int iw, Error **errp); 214 uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp); 215 216 static inline hwaddr cxl_decode_ig(int ig) 217 { 218 return 1ULL << (ig + 8); 219 } 220 221 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb); 222 223 #endif 224