1 /* 2 * QEMU CXL Component 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_COMPONENT_H 11 #define CXL_COMPONENT_H 12 13 /* CXL 2.0 - 8.2.4 */ 14 #define CXL2_COMPONENT_IO_REGION_SIZE 0x1000 15 #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000 16 #define CXL2_COMPONENT_BLOCK_SIZE 0x10000 17 18 #include "qemu/range.h" 19 #include "hw/cxl/cxl_cdat.h" 20 #include "hw/register.h" 21 #include "qapi/error.h" 22 23 enum reg_type { 24 CXL2_DEVICE, 25 CXL2_TYPE3_DEVICE, 26 CXL2_LOGICAL_DEVICE, 27 CXL2_ROOT_PORT, 28 CXL2_UPSTREAM_PORT, 29 CXL2_DOWNSTREAM_PORT 30 }; 31 32 /* 33 * Capability registers are defined at the top of the CXL.cache/mem region and 34 * are packed. For our purposes we will always define the caps in the same 35 * order. 36 * CXL 2.0 - 8.2.5 Table 142 for details. 37 */ 38 39 /* CXL 2.0 - 8.2.5.1 */ 40 REG32(CXL_CAPABILITY_HEADER, 0) 41 FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16) 42 FIELD(CXL_CAPABILITY_HEADER, VERSION, 16, 4) 43 FIELD(CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 20, 4) 44 FIELD(CXL_CAPABILITY_HEADER, ARRAY_SIZE, 24, 8) 45 46 #define CXLx_CAPABILITY_HEADER(type, offset) \ 47 REG32(CXL_##type##_CAPABILITY_HEADER, offset) \ 48 FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \ 49 FIELD(CXL_##type##_CAPABILITY_HEADER, VERSION, 16, 4) \ 50 FIELD(CXL_##type##_CAPABILITY_HEADER, PTR, 20, 12) 51 CXLx_CAPABILITY_HEADER(RAS, 0x4) 52 CXLx_CAPABILITY_HEADER(LINK, 0x8) 53 CXLx_CAPABILITY_HEADER(HDM, 0xc) 54 CXLx_CAPABILITY_HEADER(EXTSEC, 0x10) 55 CXLx_CAPABILITY_HEADER(SNOOP, 0x14) 56 57 /* 58 * Capability structures contain the actual registers that the CXL component 59 * implements. Some of these are specific to certain types of components, but 60 * this implementation leaves enough space regardless. 61 */ 62 /* 8.2.5.9 - CXL RAS Capability Structure */ 63 64 /* Give ample space for caps before this */ 65 #define CXL_RAS_REGISTERS_OFFSET 0x80 66 #define CXL_RAS_REGISTERS_SIZE 0x58 67 REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET) 68 #define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0 69 #define CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY 1 70 #define CXL_RAS_UNC_ERR_CACHE_BE_PARITY 2 71 #define CXL_RAS_UNC_ERR_CACHE_DATA_ECC 3 72 #define CXL_RAS_UNC_ERR_MEM_DATA_PARITY 4 73 #define CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY 5 74 #define CXL_RAS_UNC_ERR_MEM_BE_PARITY 6 75 #define CXL_RAS_UNC_ERR_MEM_DATA_ECC 7 76 #define CXL_RAS_UNC_ERR_REINIT_THRESHOLD 8 77 #define CXL_RAS_UNC_ERR_RSVD_ENCODING 9 78 #define CXL_RAS_UNC_ERR_POISON_RECEIVED 10 79 #define CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW 11 80 #define CXL_RAS_UNC_ERR_INTERNAL 14 81 #define CXL_RAS_UNC_ERR_CXL_IDE_TX 15 82 #define CXL_RAS_UNC_ERR_CXL_IDE_RX 16 83 #define CXL_RAS_UNC_ERR_CXL_UNUSED 63 /* Magic value */ 84 REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4) 85 REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8) 86 REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc) 87 #define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0 88 #define CXL_RAS_COR_ERR_MEM_DATA_ECC 1 89 #define CXL_RAS_COR_ERR_CRC_THRESHOLD 2 90 #define CXL_RAS_COR_ERR_RETRY_THRESHOLD 3 91 #define CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED 4 92 #define CXL_RAS_COR_ERR_MEM_POISON_RECEIVED 5 93 #define CXL_RAS_COR_ERR_PHYSICAL 6 94 REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10) 95 REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14) 96 FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6) 97 REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) 98 #define CXL_RAS_ERR_HEADER_NUM 32 99 /* Offset 0x18 - 0x58 reserved for RAS logs */ 100 101 /* 8.2.5.10 - CXL Security Capability Structure */ 102 #define CXL_SEC_REGISTERS_OFFSET \ 103 (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE) 104 #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */ 105 106 /* 8.2.5.11 - CXL Link Capability Structure */ 107 #define CXL_LINK_REGISTERS_OFFSET \ 108 (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE) 109 #define CXL_LINK_REGISTERS_SIZE 0x38 110 111 /* 8.2.5.12 - CXL HDM Decoder Capability Structure */ 112 #define HDM_DECODE_MAX 10 /* 8.2.5.12.1 */ 113 #define CXL_HDM_REGISTERS_OFFSET \ 114 (CXL_LINK_REGISTERS_OFFSET + CXL_LINK_REGISTERS_SIZE) 115 #define CXL_HDM_REGISTERS_SIZE (0x10 + 0x20 * HDM_DECODE_MAX) 116 #define HDM_DECODER_INIT(n) \ 117 REG32(CXL_HDM_DECODER##n##_BASE_LO, \ 118 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) \ 119 FIELD(CXL_HDM_DECODER##n##_BASE_LO, L, 28, 4) \ 120 REG32(CXL_HDM_DECODER##n##_BASE_HI, \ 121 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) \ 122 REG32(CXL_HDM_DECODER##n##_SIZE_LO, \ 123 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) \ 124 REG32(CXL_HDM_DECODER##n##_SIZE_HI, \ 125 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) \ 126 REG32(CXL_HDM_DECODER##n##_CTRL, \ 127 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x20) \ 128 FIELD(CXL_HDM_DECODER##n##_CTRL, IG, 0, 4) \ 129 FIELD(CXL_HDM_DECODER##n##_CTRL, IW, 4, 4) \ 130 FIELD(CXL_HDM_DECODER##n##_CTRL, LOCK_ON_COMMIT, 8, 1) \ 131 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMIT, 9, 1) \ 132 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMITTED, 10, 1) \ 133 FIELD(CXL_HDM_DECODER##n##_CTRL, ERR, 11, 1) \ 134 FIELD(CXL_HDM_DECODER##n##_CTRL, TYPE, 12, 1) \ 135 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_LO, \ 136 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ 137 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_HI, \ 138 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) 139 140 REG32(CXL_HDM_DECODER_CAPABILITY, CXL_HDM_REGISTERS_OFFSET) 141 FIELD(CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 0, 4) 142 FIELD(CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 4, 4) 143 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 8, 1) 144 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 9, 1) 145 FIELD(CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 10, 1) 146 REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4) 147 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1) 148 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1) 149 150 HDM_DECODER_INIT(0); 151 152 /* 8.2.5.13 - CXL Extended Security Capability Structure (Root complex only) */ 153 #define EXTSEC_ENTRY_MAX 256 154 #define CXL_EXTSEC_REGISTERS_OFFSET \ 155 (CXL_HDM_REGISTERS_OFFSET + CXL_HDM_REGISTERS_SIZE) 156 #define CXL_EXTSEC_REGISTERS_SIZE (8 * EXTSEC_ENTRY_MAX + 4) 157 158 /* 8.2.5.14 - CXL IDE Capability Structure */ 159 #define CXL_IDE_REGISTERS_OFFSET \ 160 (CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC_REGISTERS_SIZE) 161 #define CXL_IDE_REGISTERS_SIZE 0x20 162 163 /* 8.2.5.15 - CXL Snoop Filter Capability Structure */ 164 #define CXL_SNOOP_REGISTERS_OFFSET \ 165 (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE) 166 #define CXL_SNOOP_REGISTERS_SIZE 0x8 167 168 QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) >= 0x1000, 169 "No space for registers"); 170 171 typedef struct component_registers { 172 /* 173 * Main memory region to be registered with QEMU core. 174 */ 175 MemoryRegion component_registers; 176 177 /* 178 * 8.2.4 Table 141: 179 * 0x0000 - 0x0fff CXL.io registers 180 * 0x1000 - 0x1fff CXL.cache and CXL.mem 181 * 0x2000 - 0xdfff Implementation specific 182 * 0xe000 - 0xe3ff CXL ARB/MUX registers 183 * 0xe400 - 0xffff RSVD 184 */ 185 uint32_t io_registers[CXL2_COMPONENT_IO_REGION_SIZE >> 2]; 186 MemoryRegion io; 187 188 uint32_t cache_mem_registers[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 189 uint32_t cache_mem_regs_write_mask[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 190 MemoryRegion cache_mem; 191 192 MemoryRegion impl_specific; 193 MemoryRegion arb_mux; 194 MemoryRegion rsvd; 195 196 /* special_ops is used for any component that needs any specific handling */ 197 MemoryRegionOps *special_ops; 198 } ComponentRegisters; 199 200 /* 201 * A CXL component represents all entities in a CXL hierarchy. This includes, 202 * host bridges, root ports, upstream/downstream switch ports, and devices 203 */ 204 typedef struct cxl_component { 205 ComponentRegisters crb; 206 union { 207 struct { 208 Range dvsecs[CXL20_MAX_DVSEC]; 209 uint16_t dvsec_offset; 210 struct PCIDevice *pdev; 211 }; 212 }; 213 214 CDATObject cdat; 215 } CXLComponentState; 216 217 void cxl_component_register_block_init(Object *obj, 218 CXLComponentState *cxl_cstate, 219 const char *type); 220 void cxl_component_register_init_common(uint32_t *reg_state, 221 uint32_t *write_msk, 222 enum reg_type type); 223 224 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, 225 enum reg_type cxl_dev_type, uint16_t length, 226 uint16_t type, uint8_t rev, uint8_t *body); 227 228 static inline int cxl_decoder_count_enc(int count) 229 { 230 switch (count) { 231 case 1: return 0; 232 case 2: return 1; 233 case 4: return 2; 234 case 6: return 3; 235 case 8: return 4; 236 case 10: return 5; 237 } 238 return 0; 239 } 240 241 uint8_t cxl_interleave_ways_enc(int iw, Error **errp); 242 uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp); 243 244 static inline hwaddr cxl_decode_ig(int ig) 245 { 246 return 1ULL << (ig + 8); 247 } 248 249 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb); 250 bool cxl_get_hb_passthrough(PCIHostState *hb); 251 252 void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp); 253 void cxl_doe_cdat_release(CXLComponentState *cxl_cstate); 254 void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp); 255 256 #endif 257