1 /* 2 * QEMU CXL Component 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_COMPONENT_H 11 #define CXL_COMPONENT_H 12 13 /* CXL r3.1 Section 8.2.4: CXL.cache and CXL.mem Registers */ 14 #define CXL2_COMPONENT_IO_REGION_SIZE 0x1000 15 #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000 16 #define CXL2_COMPONENT_BLOCK_SIZE 0x10000 17 18 #include "qemu/range.h" 19 #include "hw/cxl/cxl_cdat.h" 20 #include "hw/register.h" 21 #include "qapi/error.h" 22 23 enum reg_type { 24 CXL2_DEVICE, 25 CXL2_TYPE3_DEVICE, 26 CXL2_LOGICAL_DEVICE, 27 CXL2_ROOT_PORT, 28 CXL2_UPSTREAM_PORT, 29 CXL2_DOWNSTREAM_PORT, 30 CXL3_SWITCH_MAILBOX_CCI, 31 }; 32 33 /* 34 * Capability registers are defined at the top of the CXL.cache/mem region and 35 * are packed. For our purposes we will always define the caps in the same 36 * order. 37 * CXL r3.1 Table 8-22: CXL_CAPABILITY_ID Assignment for details. 38 */ 39 40 /* CXL r3.1 Section 8.2.4.1: CXL Capability Header Register */ 41 #define CXL_CAPABILITY_VERSION 1 42 REG32(CXL_CAPABILITY_HEADER, 0) 43 FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16) 44 FIELD(CXL_CAPABILITY_HEADER, VERSION, 16, 4) 45 FIELD(CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 20, 4) 46 FIELD(CXL_CAPABILITY_HEADER, ARRAY_SIZE, 24, 8) 47 48 #define CXLx_CAPABILITY_HEADER(type, offset) \ 49 REG32(CXL_##type##_CAPABILITY_HEADER, offset) \ 50 FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \ 51 FIELD(CXL_##type##_CAPABILITY_HEADER, VERSION, 16, 4) \ 52 FIELD(CXL_##type##_CAPABILITY_HEADER, PTR, 20, 12) 53 CXLx_CAPABILITY_HEADER(RAS, 0x4) 54 CXLx_CAPABILITY_HEADER(LINK, 0x8) 55 CXLx_CAPABILITY_HEADER(HDM, 0xc) 56 CXLx_CAPABILITY_HEADER(EXTSEC, 0x10) 57 CXLx_CAPABILITY_HEADER(SNOOP, 0x14) 58 59 /* 60 * Capability structures contain the actual registers that the CXL component 61 * implements. Some of these are specific to certain types of components, but 62 * this implementation leaves enough space regardless. 63 */ 64 65 /* CXL r3.1 Section 8.2.4.17: CXL RAS Capability Structure */ 66 #define CXL_RAS_CAPABILITY_VERSION 3 67 /* Give ample space for caps before this */ 68 #define CXL_RAS_REGISTERS_OFFSET 0x80 69 #define CXL_RAS_REGISTERS_SIZE 0x58 70 REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET) 71 #define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0 72 #define CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY 1 73 #define CXL_RAS_UNC_ERR_CACHE_BE_PARITY 2 74 #define CXL_RAS_UNC_ERR_CACHE_DATA_ECC 3 75 #define CXL_RAS_UNC_ERR_MEM_DATA_PARITY 4 76 #define CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY 5 77 #define CXL_RAS_UNC_ERR_MEM_BE_PARITY 6 78 #define CXL_RAS_UNC_ERR_MEM_DATA_ECC 7 79 #define CXL_RAS_UNC_ERR_REINIT_THRESHOLD 8 80 #define CXL_RAS_UNC_ERR_RSVD_ENCODING 9 81 #define CXL_RAS_UNC_ERR_POISON_RECEIVED 10 82 #define CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW 11 83 #define CXL_RAS_UNC_ERR_INTERNAL 14 84 #define CXL_RAS_UNC_ERR_CXL_IDE_TX 15 85 #define CXL_RAS_UNC_ERR_CXL_IDE_RX 16 86 #define CXL_RAS_UNC_ERR_CXL_UNUSED 63 /* Magic value */ 87 REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4) 88 REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8) 89 REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc) 90 #define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0 91 #define CXL_RAS_COR_ERR_MEM_DATA_ECC 1 92 #define CXL_RAS_COR_ERR_CRC_THRESHOLD 2 93 #define CXL_RAS_COR_ERR_RETRY_THRESHOLD 3 94 #define CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED 4 95 #define CXL_RAS_COR_ERR_MEM_POISON_RECEIVED 5 96 #define CXL_RAS_COR_ERR_PHYSICAL 6 97 REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10) 98 REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14) 99 FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6) 100 FIELD(CXL_RAS_ERR_CAP_CTRL, MULTIPLE_HEADER_RECORDING_CAP, 9, 1) 101 FIELD(CXL_RAS_ERR_POISON_ENABLED, POISON_ENABLED, 13, 1) 102 REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) 103 #define CXL_RAS_ERR_HEADER_NUM 32 104 /* Offset 0x18 - 0x58 reserved for RAS logs */ 105 106 /* CXL r3.1 Section 8.2.4.18: CXL Security Capability Structure */ 107 #define CXL_SEC_REGISTERS_OFFSET \ 108 (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE) 109 #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */ 110 111 /* CXL r3.1 Section 8.2.4.19: CXL Link Capability Structure */ 112 #define CXL_LINK_CAPABILITY_VERSION 2 113 #define CXL_LINK_REGISTERS_OFFSET \ 114 (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE) 115 #define CXL_LINK_REGISTERS_SIZE 0x50 116 117 /* CXL r3.1 Section 8.2.4.20: CXL HDM Decoder Capability Structure */ 118 #define HDM_DECODE_MAX 10 /* Maximum decoders for Devices */ 119 #define CXL_HDM_CAPABILITY_VERSION 3 120 #define CXL_HDM_REGISTERS_OFFSET \ 121 (CXL_LINK_REGISTERS_OFFSET + CXL_LINK_REGISTERS_SIZE) 122 #define CXL_HDM_REGISTERS_SIZE (0x10 + 0x20 * HDM_DECODE_MAX) 123 #define HDM_DECODER_INIT(n) \ 124 REG32(CXL_HDM_DECODER##n##_BASE_LO, \ 125 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) \ 126 FIELD(CXL_HDM_DECODER##n##_BASE_LO, L, 28, 4) \ 127 REG32(CXL_HDM_DECODER##n##_BASE_HI, \ 128 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) \ 129 REG32(CXL_HDM_DECODER##n##_SIZE_LO, \ 130 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) \ 131 REG32(CXL_HDM_DECODER##n##_SIZE_HI, \ 132 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) \ 133 REG32(CXL_HDM_DECODER##n##_CTRL, \ 134 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x20) \ 135 FIELD(CXL_HDM_DECODER##n##_CTRL, IG, 0, 4) \ 136 FIELD(CXL_HDM_DECODER##n##_CTRL, IW, 4, 4) \ 137 FIELD(CXL_HDM_DECODER##n##_CTRL, LOCK_ON_COMMIT, 8, 1) \ 138 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMIT, 9, 1) \ 139 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMITTED, 10, 1) \ 140 FIELD(CXL_HDM_DECODER##n##_CTRL, ERR, 11, 1) \ 141 FIELD(CXL_HDM_DECODER##n##_CTRL, TYPE, 12, 1) \ 142 FIELD(CXL_HDM_DECODER##n##_CTRL, BI, 13, 1) \ 143 FIELD(CXL_HDM_DECODER##n##_CTRL, UIO, 14, 1) \ 144 FIELD(CXL_HDM_DECODER##n##_CTRL, UIG, 16, 4) \ 145 FIELD(CXL_HDM_DECODER##n##_CTRL, UIW, 20, 4) \ 146 FIELD(CXL_HDM_DECODER##n##_CTRL, ISP, 24, 4) \ 147 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_LO, \ 148 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ 149 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_HI, \ 150 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) \ 151 REG32(CXL_HDM_DECODER##n##_DPA_SKIP_LO, \ 152 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ 153 REG32(CXL_HDM_DECODER##n##_DPA_SKIP_HI, \ 154 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) 155 156 REG32(CXL_HDM_DECODER_CAPABILITY, CXL_HDM_REGISTERS_OFFSET) 157 FIELD(CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 0, 4) 158 FIELD(CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 4, 4) 159 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 8, 1) 160 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 9, 1) 161 FIELD(CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 10, 1) 162 FIELD(CXL_HDM_DECODER_CAPABILITY, 3_6_12_WAY, 11, 1) 163 FIELD(CXL_HDM_DECODER_CAPABILITY, 16_WAY, 12, 1) 164 FIELD(CXL_HDM_DECODER_CAPABILITY, UIO, 13, 1) 165 FIELD(CXL_HDM_DECODER_CAPABILITY, UIO_DECODER_COUNT, 16, 4) 166 FIELD(CXL_HDM_DECODER_CAPABILITY, MEMDATA_NXM_CAP, 20, 1) 167 FIELD(CXL_HDM_DECODER_CAPABILITY, SUPPORTED_COHERENCY_MODEL, 21, 2) 168 REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4) 169 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1) 170 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1) 171 172 /* Support 4 decoders at all levels of topology */ 173 #define CXL_HDM_DECODER_COUNT 4 174 175 HDM_DECODER_INIT(0); 176 HDM_DECODER_INIT(1); 177 HDM_DECODER_INIT(2); 178 HDM_DECODER_INIT(3); 179 180 /* 181 * CXL r3.1 Section 8.2.4.21: CXL Extended Security Capability Structure 182 * (Root complex only) 183 */ 184 #define EXTSEC_ENTRY_MAX 256 185 #define CXL_EXTSEC_CAP_VERSION 2 186 #define CXL_EXTSEC_REGISTERS_OFFSET \ 187 (CXL_HDM_REGISTERS_OFFSET + CXL_HDM_REGISTERS_SIZE) 188 #define CXL_EXTSEC_REGISTERS_SIZE (8 * EXTSEC_ENTRY_MAX + 4) 189 190 /* CXL r3.1 Section 8.2.4.22: CXL IDE Capability Structure */ 191 #define CXL_IDE_CAP_VERSION 2 192 #define CXL_IDE_REGISTERS_OFFSET \ 193 (CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC_REGISTERS_SIZE) 194 #define CXL_IDE_REGISTERS_SIZE 0x24 195 196 /* CXL r3.1 Section 8.2.4.23 - CXL Snoop Filter Capability Structure */ 197 #define CXL_SNOOP_CAP_VERSION 1 198 #define CXL_SNOOP_REGISTERS_OFFSET \ 199 (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE) 200 #define CXL_SNOOP_REGISTERS_SIZE 0x8 201 202 QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + 203 CXL_SNOOP_REGISTERS_SIZE) >= 0x1000, 204 "No space for registers"); 205 206 typedef struct component_registers { 207 /* 208 * Main memory region to be registered with QEMU core. 209 */ 210 MemoryRegion component_registers; 211 212 /* 213 * CXL r3.1 Table 8-21: CXL Subsystem Component Register Ranges 214 * 0x0000 - 0x0fff CXL.io registers 215 * 0x1000 - 0x1fff CXL.cache and CXL.mem 216 * 0x2000 - 0xdfff Implementation specific 217 * 0xe000 - 0xe3ff CXL ARB/MUX registers 218 * 0xe400 - 0xffff RSVD 219 */ 220 uint32_t io_registers[CXL2_COMPONENT_IO_REGION_SIZE >> 2]; 221 MemoryRegion io; 222 223 uint32_t cache_mem_registers[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 224 uint32_t cache_mem_regs_write_mask[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 225 MemoryRegion cache_mem; 226 227 MemoryRegion impl_specific; 228 MemoryRegion arb_mux; 229 MemoryRegion rsvd; 230 231 /* special_ops is used for any component that needs any specific handling */ 232 MemoryRegionOps *special_ops; 233 } ComponentRegisters; 234 235 /* 236 * A CXL component represents all entities in a CXL hierarchy. This includes, 237 * host bridges, root ports, upstream/downstream switch ports, and devices 238 */ 239 typedef struct cxl_component { 240 ComponentRegisters crb; 241 union { 242 struct { 243 Range dvsecs[CXL20_MAX_DVSEC]; 244 uint16_t dvsec_offset; 245 struct PCIDevice *pdev; 246 }; 247 }; 248 249 CDATObject cdat; 250 } CXLComponentState; 251 252 void cxl_component_register_block_init(Object *obj, 253 CXLComponentState *cxl_cstate, 254 const char *type); 255 void cxl_component_register_init_common(uint32_t *reg_state, 256 uint32_t *write_msk, 257 enum reg_type type); 258 259 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, 260 enum reg_type cxl_dev_type, uint16_t length, 261 uint16_t type, uint8_t rev, uint8_t *body); 262 263 int cxl_decoder_count_enc(int count); 264 int cxl_decoder_count_dec(int enc_cnt); 265 266 uint8_t cxl_interleave_ways_enc(int iw, Error **errp); 267 int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp); 268 uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp); 269 270 hwaddr cxl_decode_ig(int ig); 271 272 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb); 273 bool cxl_get_hb_passthrough(PCIHostState *hb); 274 275 void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp); 276 void cxl_doe_cdat_release(CXLComponentState *cxl_cstate); 277 void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp); 278 279 #endif 280