1 /* 2 * QEMU CXL Component 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_COMPONENT_H 11 #define CXL_COMPONENT_H 12 13 /* CXL 2.0 - 8.2.4 */ 14 #define CXL2_COMPONENT_IO_REGION_SIZE 0x1000 15 #define CXL2_COMPONENT_CM_REGION_SIZE 0x1000 16 #define CXL2_COMPONENT_BLOCK_SIZE 0x10000 17 18 #include "qemu/range.h" 19 #include "hw/cxl/cxl_cdat.h" 20 #include "hw/register.h" 21 #include "qapi/error.h" 22 23 enum reg_type { 24 CXL2_DEVICE, 25 CXL2_TYPE3_DEVICE, 26 CXL2_LOGICAL_DEVICE, 27 CXL2_ROOT_PORT, 28 CXL2_UPSTREAM_PORT, 29 CXL2_DOWNSTREAM_PORT 30 }; 31 32 /* 33 * Capability registers are defined at the top of the CXL.cache/mem region and 34 * are packed. For our purposes we will always define the caps in the same 35 * order. 36 * CXL 2.0 - 8.2.5 Table 142 for details. 37 */ 38 39 /* CXL 2.0 - 8.2.5.1 */ 40 REG32(CXL_CAPABILITY_HEADER, 0) 41 FIELD(CXL_CAPABILITY_HEADER, ID, 0, 16) 42 FIELD(CXL_CAPABILITY_HEADER, VERSION, 16, 4) 43 FIELD(CXL_CAPABILITY_HEADER, CACHE_MEM_VERSION, 20, 4) 44 FIELD(CXL_CAPABILITY_HEADER, ARRAY_SIZE, 24, 8) 45 46 #define CXLx_CAPABILITY_HEADER(type, offset) \ 47 REG32(CXL_##type##_CAPABILITY_HEADER, offset) \ 48 FIELD(CXL_##type##_CAPABILITY_HEADER, ID, 0, 16) \ 49 FIELD(CXL_##type##_CAPABILITY_HEADER, VERSION, 16, 4) \ 50 FIELD(CXL_##type##_CAPABILITY_HEADER, PTR, 20, 12) 51 CXLx_CAPABILITY_HEADER(RAS, 0x4) 52 CXLx_CAPABILITY_HEADER(LINK, 0x8) 53 CXLx_CAPABILITY_HEADER(HDM, 0xc) 54 CXLx_CAPABILITY_HEADER(EXTSEC, 0x10) 55 CXLx_CAPABILITY_HEADER(SNOOP, 0x14) 56 57 /* 58 * Capability structures contain the actual registers that the CXL component 59 * implements. Some of these are specific to certain types of components, but 60 * this implementation leaves enough space regardless. 61 */ 62 /* 8.2.5.9 - CXL RAS Capability Structure */ 63 64 /* Give ample space for caps before this */ 65 #define CXL_RAS_REGISTERS_OFFSET 0x80 66 #define CXL_RAS_REGISTERS_SIZE 0x58 67 REG32(CXL_RAS_UNC_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET) 68 #define CXL_RAS_UNC_ERR_CACHE_DATA_PARITY 0 69 #define CXL_RAS_UNC_ERR_CACHE_ADDRESS_PARITY 1 70 #define CXL_RAS_UNC_ERR_CACHE_BE_PARITY 2 71 #define CXL_RAS_UNC_ERR_CACHE_DATA_ECC 3 72 #define CXL_RAS_UNC_ERR_MEM_DATA_PARITY 4 73 #define CXL_RAS_UNC_ERR_MEM_ADDRESS_PARITY 5 74 #define CXL_RAS_UNC_ERR_MEM_BE_PARITY 6 75 #define CXL_RAS_UNC_ERR_MEM_DATA_ECC 7 76 #define CXL_RAS_UNC_ERR_REINIT_THRESHOLD 8 77 #define CXL_RAS_UNC_ERR_RSVD_ENCODING 9 78 #define CXL_RAS_UNC_ERR_POISON_RECEIVED 10 79 #define CXL_RAS_UNC_ERR_RECEIVER_OVERFLOW 11 80 #define CXL_RAS_UNC_ERR_INTERNAL 14 81 #define CXL_RAS_UNC_ERR_CXL_IDE_TX 15 82 #define CXL_RAS_UNC_ERR_CXL_IDE_RX 16 83 #define CXL_RAS_UNC_ERR_CXL_UNUSED 63 /* Magic value */ 84 REG32(CXL_RAS_UNC_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x4) 85 REG32(CXL_RAS_UNC_ERR_SEVERITY, CXL_RAS_REGISTERS_OFFSET + 0x8) 86 REG32(CXL_RAS_COR_ERR_STATUS, CXL_RAS_REGISTERS_OFFSET + 0xc) 87 #define CXL_RAS_COR_ERR_CACHE_DATA_ECC 0 88 #define CXL_RAS_COR_ERR_MEM_DATA_ECC 1 89 #define CXL_RAS_COR_ERR_CRC_THRESHOLD 2 90 #define CXL_RAS_COR_ERR_RETRY_THRESHOLD 3 91 #define CXL_RAS_COR_ERR_CACHE_POISON_RECEIVED 4 92 #define CXL_RAS_COR_ERR_MEM_POISON_RECEIVED 5 93 #define CXL_RAS_COR_ERR_PHYSICAL 6 94 REG32(CXL_RAS_COR_ERR_MASK, CXL_RAS_REGISTERS_OFFSET + 0x10) 95 REG32(CXL_RAS_ERR_CAP_CTRL, CXL_RAS_REGISTERS_OFFSET + 0x14) 96 FIELD(CXL_RAS_ERR_CAP_CTRL, FIRST_ERROR_POINTER, 0, 6) 97 REG32(CXL_RAS_ERR_HEADER0, CXL_RAS_REGISTERS_OFFSET + 0x18) 98 #define CXL_RAS_ERR_HEADER_NUM 32 99 /* Offset 0x18 - 0x58 reserved for RAS logs */ 100 101 /* 8.2.5.10 - CXL Security Capability Structure */ 102 #define CXL_SEC_REGISTERS_OFFSET \ 103 (CXL_RAS_REGISTERS_OFFSET + CXL_RAS_REGISTERS_SIZE) 104 #define CXL_SEC_REGISTERS_SIZE 0 /* We don't implement 1.1 downstream ports */ 105 106 /* 8.2.5.11 - CXL Link Capability Structure */ 107 #define CXL_LINK_REGISTERS_OFFSET \ 108 (CXL_SEC_REGISTERS_OFFSET + CXL_SEC_REGISTERS_SIZE) 109 #define CXL_LINK_REGISTERS_SIZE 0x38 110 111 /* 8.2.5.12 - CXL HDM Decoder Capability Structure */ 112 #define HDM_DECODE_MAX 10 /* 8.2.5.12.1 */ 113 #define CXL_HDM_REGISTERS_OFFSET \ 114 (CXL_LINK_REGISTERS_OFFSET + CXL_LINK_REGISTERS_SIZE) 115 #define CXL_HDM_REGISTERS_SIZE (0x10 + 0x20 * HDM_DECODE_MAX) 116 #define HDM_DECODER_INIT(n) \ 117 REG32(CXL_HDM_DECODER##n##_BASE_LO, \ 118 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x10) \ 119 FIELD(CXL_HDM_DECODER##n##_BASE_LO, L, 28, 4) \ 120 REG32(CXL_HDM_DECODER##n##_BASE_HI, \ 121 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x14) \ 122 REG32(CXL_HDM_DECODER##n##_SIZE_LO, \ 123 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x18) \ 124 REG32(CXL_HDM_DECODER##n##_SIZE_HI, \ 125 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x1C) \ 126 REG32(CXL_HDM_DECODER##n##_CTRL, \ 127 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x20) \ 128 FIELD(CXL_HDM_DECODER##n##_CTRL, IG, 0, 4) \ 129 FIELD(CXL_HDM_DECODER##n##_CTRL, IW, 4, 4) \ 130 FIELD(CXL_HDM_DECODER##n##_CTRL, LOCK_ON_COMMIT, 8, 1) \ 131 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMIT, 9, 1) \ 132 FIELD(CXL_HDM_DECODER##n##_CTRL, COMMITTED, 10, 1) \ 133 FIELD(CXL_HDM_DECODER##n##_CTRL, ERR, 11, 1) \ 134 FIELD(CXL_HDM_DECODER##n##_CTRL, TYPE, 12, 1) \ 135 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_LO, \ 136 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ 137 REG32(CXL_HDM_DECODER##n##_TARGET_LIST_HI, \ 138 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) \ 139 REG32(CXL_HDM_DECODER##n##_DPA_SKIP_LO, \ 140 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x24) \ 141 REG32(CXL_HDM_DECODER##n##_DPA_SKIP_HI, \ 142 CXL_HDM_REGISTERS_OFFSET + (0x20 * n) + 0x28) 143 144 REG32(CXL_HDM_DECODER_CAPABILITY, CXL_HDM_REGISTERS_OFFSET) 145 FIELD(CXL_HDM_DECODER_CAPABILITY, DECODER_COUNT, 0, 4) 146 FIELD(CXL_HDM_DECODER_CAPABILITY, TARGET_COUNT, 4, 4) 147 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_256B, 8, 1) 148 FIELD(CXL_HDM_DECODER_CAPABILITY, INTERLEAVE_4K, 9, 1) 149 FIELD(CXL_HDM_DECODER_CAPABILITY, POISON_ON_ERR_CAP, 10, 1) 150 REG32(CXL_HDM_DECODER_GLOBAL_CONTROL, CXL_HDM_REGISTERS_OFFSET + 4) 151 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, POISON_ON_ERR_EN, 0, 1) 152 FIELD(CXL_HDM_DECODER_GLOBAL_CONTROL, HDM_DECODER_ENABLE, 1, 1) 153 154 /* Support 4 decoders at all levels of topology */ 155 #define CXL_HDM_DECODER_COUNT 4 156 157 HDM_DECODER_INIT(0); 158 HDM_DECODER_INIT(1); 159 HDM_DECODER_INIT(2); 160 HDM_DECODER_INIT(3); 161 162 /* 8.2.5.13 - CXL Extended Security Capability Structure (Root complex only) */ 163 #define EXTSEC_ENTRY_MAX 256 164 #define CXL_EXTSEC_REGISTERS_OFFSET \ 165 (CXL_HDM_REGISTERS_OFFSET + CXL_HDM_REGISTERS_SIZE) 166 #define CXL_EXTSEC_REGISTERS_SIZE (8 * EXTSEC_ENTRY_MAX + 4) 167 168 /* 8.2.5.14 - CXL IDE Capability Structure */ 169 #define CXL_IDE_REGISTERS_OFFSET \ 170 (CXL_EXTSEC_REGISTERS_OFFSET + CXL_EXTSEC_REGISTERS_SIZE) 171 #define CXL_IDE_REGISTERS_SIZE 0x20 172 173 /* 8.2.5.15 - CXL Snoop Filter Capability Structure */ 174 #define CXL_SNOOP_REGISTERS_OFFSET \ 175 (CXL_IDE_REGISTERS_OFFSET + CXL_IDE_REGISTERS_SIZE) 176 #define CXL_SNOOP_REGISTERS_SIZE 0x8 177 178 QEMU_BUILD_BUG_MSG((CXL_SNOOP_REGISTERS_OFFSET + CXL_SNOOP_REGISTERS_SIZE) >= 0x1000, 179 "No space for registers"); 180 181 typedef struct component_registers { 182 /* 183 * Main memory region to be registered with QEMU core. 184 */ 185 MemoryRegion component_registers; 186 187 /* 188 * 8.2.4 Table 141: 189 * 0x0000 - 0x0fff CXL.io registers 190 * 0x1000 - 0x1fff CXL.cache and CXL.mem 191 * 0x2000 - 0xdfff Implementation specific 192 * 0xe000 - 0xe3ff CXL ARB/MUX registers 193 * 0xe400 - 0xffff RSVD 194 */ 195 uint32_t io_registers[CXL2_COMPONENT_IO_REGION_SIZE >> 2]; 196 MemoryRegion io; 197 198 uint32_t cache_mem_registers[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 199 uint32_t cache_mem_regs_write_mask[CXL2_COMPONENT_CM_REGION_SIZE >> 2]; 200 MemoryRegion cache_mem; 201 202 MemoryRegion impl_specific; 203 MemoryRegion arb_mux; 204 MemoryRegion rsvd; 205 206 /* special_ops is used for any component that needs any specific handling */ 207 MemoryRegionOps *special_ops; 208 } ComponentRegisters; 209 210 /* 211 * A CXL component represents all entities in a CXL hierarchy. This includes, 212 * host bridges, root ports, upstream/downstream switch ports, and devices 213 */ 214 typedef struct cxl_component { 215 ComponentRegisters crb; 216 union { 217 struct { 218 Range dvsecs[CXL20_MAX_DVSEC]; 219 uint16_t dvsec_offset; 220 struct PCIDevice *pdev; 221 }; 222 }; 223 224 CDATObject cdat; 225 } CXLComponentState; 226 227 void cxl_component_register_block_init(Object *obj, 228 CXLComponentState *cxl_cstate, 229 const char *type); 230 void cxl_component_register_init_common(uint32_t *reg_state, 231 uint32_t *write_msk, 232 enum reg_type type); 233 234 void cxl_component_create_dvsec(CXLComponentState *cxl_cstate, 235 enum reg_type cxl_dev_type, uint16_t length, 236 uint16_t type, uint8_t rev, uint8_t *body); 237 238 int cxl_decoder_count_enc(int count); 239 int cxl_decoder_count_dec(int enc_cnt); 240 241 uint8_t cxl_interleave_ways_enc(int iw, Error **errp); 242 int cxl_interleave_ways_dec(uint8_t iw_enc, Error **errp); 243 uint8_t cxl_interleave_granularity_enc(uint64_t gran, Error **errp); 244 245 hwaddr cxl_decode_ig(int ig); 246 247 CXLComponentState *cxl_get_hb_cstate(PCIHostState *hb); 248 bool cxl_get_hb_passthrough(PCIHostState *hb); 249 250 void cxl_doe_cdat_init(CXLComponentState *cxl_cstate, Error **errp); 251 void cxl_doe_cdat_release(CXLComponentState *cxl_cstate); 252 void cxl_doe_cdat_update(CXLComponentState *cxl_cstate, Error **errp); 253 254 #endif 255