1 /* 2 * QEMU CXL Support 3 * 4 * Copyright (c) 2020 Intel 5 * 6 * This work is licensed under the terms of the GNU GPL, version 2. See the 7 * COPYING file in the top-level directory. 8 */ 9 10 #ifndef CXL_H 11 #define CXL_H 12 13 14 #include "qapi/qapi-types-machine.h" 15 #include "qapi/qapi-visit-machine.h" 16 #include "hw/pci/pci_host.h" 17 #include "cxl_pci.h" 18 #include "cxl_component.h" 19 #include "cxl_device.h" 20 21 #define CXL_CACHE_LINE_SIZE 64 22 #define CXL_COMPONENT_REG_BAR_IDX 0 23 #define CXL_DEVICE_REG_BAR_IDX 2 24 25 #define CXL_WINDOW_MAX 10 26 27 typedef struct PXBCXLDev PXBCXLDev; 28 29 typedef struct CXLFixedWindow { 30 SysBusDevice parent_obj; 31 int index; 32 uint64_t size; 33 char **targets; 34 PXBCXLDev *target_hbs[16]; 35 uint8_t num_targets; 36 uint8_t enc_int_ways; 37 uint8_t enc_int_gran; 38 /* Todo: XOR based interleaving */ 39 MemoryRegion mr; 40 hwaddr base; 41 } CXLFixedWindow; 42 #define TYPE_CXL_FMW "cxl-fmw" 43 OBJECT_DECLARE_SIMPLE_TYPE(CXLFixedWindow, CXL_FMW) 44 45 typedef struct CXLState { 46 bool is_enabled; 47 MemoryRegion host_mr; 48 unsigned int next_mr_idx; 49 CXLFixedMemoryWindowOptionsList *cfmw_list; 50 } CXLState; 51 52 struct CXLHost { 53 PCIHostState parent_obj; 54 55 CXLComponentState cxl_cstate; 56 bool passthrough; 57 }; 58 59 #define TYPE_PXB_CXL_HOST "pxb-cxl-host" 60 OBJECT_DECLARE_SIMPLE_TYPE(CXLHost, PXB_CXL_HOST) 61 62 #define TYPE_CXL_USP "cxl-upstream" 63 64 typedef struct CXLUpstreamPort CXLUpstreamPort; 65 DECLARE_INSTANCE_CHECKER(CXLUpstreamPort, CXL_USP, TYPE_CXL_USP) 66 CXLComponentState *cxl_usp_to_cstate(CXLUpstreamPort *usp); 67 68 #define TYPE_CXL_DSP "cxl-downstream" 69 70 typedef struct CXLDownstreamPort CXLDownstreamPort; 71 DECLARE_INSTANCE_CHECKER(CXLDownstreamPort, CXL_DSP, TYPE_CXL_DSP) 72 73 #endif 74